Docs: Update for release FEX-2309

Merge pull request #3057 from Sonicadvance1/support_procfs_interpreter
FEXInterpreter: Supports procfs/interpreter
2026-10-17 22:00:37 +02:00 · 2023-09-05 22:16:35 -07:00 · 2023-09-05 21:53:45 -07:00 · 2023-09-05 21:30:47 -07:00 · 2023-09-05 19:43:52 -07:00 · 2023-09-05 16:35:12 -04:00
1151 changed files with 171726 additions and 37937 deletions
@@ -14,6 +14,7 @@ env:
  CC: clang
  CXX: clang++
  FEX_FORCE32BITALLOCATOR: 1
+  FEX_ENABLEAVX: 1

 jobs:
  build:
@@ -24,7 +25,7 @@ jobs:
      fail-fast: false

    steps:
-    - uses: actions/checkout@v2
+    - uses: actions/checkout@v3

    - name: Set runner label
      run: echo "runner_label=${{ matrix.arch[1] }}" >> $GITHUB_ENV
@@ -72,6 +73,11 @@ jobs:
      # Execute the build.  You can specify a specific target with "--target <NAME>"
      run: cmake --build . --config $BUILD_TYPE

+    - name: Install
+      working-directory: ${{runner.workspace}}/build
+      shell: bash
+      run: cmake --build . --config $BUILD_TYPE --target install
+
    - name: ASM Tests
      working-directory: ${{runner.workspace}}/build
      shell: bash
@@ -166,6 +172,28 @@ jobs:
      working-directory: ${{runner.workspace}}/build
      run: mv ${{runner.workspace}}/build/Testing/Temporary/LastTest.log ${{runner.workspace}}/build/Testing/Temporary/LastTest_APITests.log || true

+    - name: FEXCore APITest tests
+      working-directory: ${{runner.workspace}}/build
+      shell: bash
+      run: cmake --build . --config $BUILD_TYPE --target fexcore_apitests
+
+    - name: FEXCore APITest Test Results move
+      if: ${{ always() }}
+      shell: bash
+      working-directory: ${{runner.workspace}}/build
+      run: mv ${{runner.workspace}}/build/Testing/Temporary/LastTest.log ${{runner.workspace}}/build/Testing/Temporary/LastTest_FEXCoreAPITests.log || true
+
+    - name: ARMEmitter tests
+      working-directory: ${{runner.workspace}}/build
+      shell: bash
+      run: cmake --build . --config $BUILD_TYPE --target emitter_tests
+
+    - name: ARMEmitter Test Results move
+      if: ${{ always() }}
+      shell: bash
+      working-directory: ${{runner.workspace}}/build
+      run: mv ${{runner.workspace}}/build/Testing/Temporary/LastTest.log ${{runner.workspace}}/build/Testing/Temporary/LastTest_ARMEmitterTests.log || true
+
    - name: FEXLinuxTests
      working-directory: ${{runner.workspace}}/build
      shell: bash
@@ -188,12 +216,6 @@ jobs:
      working-directory: ${{runner.workspace}}/build
      run: mv ${{runner.workspace}}/build/Testing/Temporary/LastTest.log ${{runner.workspace}}/build/Testing/Temporary/LastTest_ThunkgenTests.log || true

-    - name: Install
-      if: matrix.arch[1] == 'x64'
-      working-directory: ${{runner.workspace}}/build
-      shell: bash
-      run: cmake --build . --config $BUILD_TYPE --target install
-
    - name: Test GL No-Thunks
      if: matrix.arch[1] == 'x64'
      working-directory: ${{runner.workspace}}/build
@@ -230,13 +252,20 @@ jobs:
      # ASM tests get quite close to 10MB
      run: truncate --size=<20M ${{runner.workspace}}/build/Testing/Temporary/LastTest_*.log || true

+    - name: Remove old SHM regions
+      if: ${{ always() }}
+      shell: bash
+      working-directory: ${{runner.workspace}}/build
+      run: cmake --build . --config $BUILD_TYPE --target remove_old_shm_regions
+
    - name: Set runner name
      if: ${{ always() }}
      run: echo "runner_name=$(hostname)" >> $GITHUB_ENV

    - name: Upload results
      if: ${{ always() }}
-      uses: 'actions/upload-artifact@v2'
+      uses: 'actions/upload-artifact@v3'
+      timeout-minutes: 1
      with:
        name: Results-${{ env.runner_name }}
        path: ${{runner.workspace}}/build/Testing/Temporary/LastTest_*.log
@@ -0,0 +1,208 @@
+name: GLIBC fault test
+# This workflow file is the same as the `Build + Test` with some key differences
+# - Runs on any x86 and ARM64 runner
+# - Disables the glibc jemalloc compile option
+# - Enables the glibc allocator fault option
+# - Disables gvisor tests to reduce stress on CI machines (tmp/shm tests overwhelm them)
+# - Disables thunk tests since they are incompatible with glibc fault allocator
+# - Disables ARMEmitter tests (We don't want to fault test vixl's disassembler)
+
+on:
+  push:
+    branches:
+      - main
+  pull_request:
+    branches:
+      - main
+
+env:
+  # Customize the CMake build type here (Release, Debug, RelWithDebInfo, etc.)
+  BUILD_TYPE: Release
+  CC: clang
+  CXX: clang++
+  FEX_FORCE32BITALLOCATOR: 1
+  FEX_ENABLEAVX: 1
+
+jobs:
+  build:
+    runs-on: ${{ matrix.arch }}
+    strategy:
+      matrix:
+        # Run on an x86 device and any ARM runner.
+        arch: [[self-hosted, x64], [self-hosted, ARM64]]
+      fail-fast: false
+
+    steps:
+    - uses: actions/checkout@v3
+
+    - name: Set runner label
+      run: echo "runner_label=${{ matrix.arch[1] }}" >> $GITHUB_ENV
+
+    - name: Set rootfs paths
+      run: |
+        echo "FEX_ROOTFS_MOUNT=/mnt/AutoNFS/rootfs/" >> $GITHUB_ENV
+        echo "FEX_ROOTFS_PATH=$HOME/Rootfs/" >> $GITHUB_ENV
+        echo "FEX_ROOTFS=$HOME/Rootfs/" >> $GITHUB_ENV
+        echo "ROOTFS=$HOME/Rootfs/" >> $GITHUB_ENV
+
+    - name: Update RootFS cache
+      # Use a bash shell so we can use the same syntax for environment variable
+      # access regardless of the host operating system
+      shell: bash
+      run: $GITHUB_WORKSPACE/Scripts/CI_FetchRootFS.py
+
+    - name : submodule checkout
+      # Need to update submodules
+      run: |
+        git submodule sync --recursive
+        git submodule update --init --depth 1
+
+    - name: Clean Build Environment
+      run: rm -Rf ${{runner.workspace}}/build
+
+    - name: Create Build Environment
+      # Some projects don't allow in-source building, so create a separate build directory
+      # We'll use this as our working directory for all subsequent commands
+      run: cmake -E make_directory ${{runner.workspace}}/build
+
+    - name: Configure CMake
+      # Use a bash shell so we can use the same syntax for environment variable
+      # access regardless of the host operating system
+      shell: bash
+      working-directory: ${{runner.workspace}}/build
+      # Note the current convention is to use the -S and -B options here to specify source
+      # and build directories, but this is only available with CMake 3.13 and higher.
+      # The CMake binaries on the Github Actions machines are (as of this writing) 3.12
+      run: cmake $GITHUB_WORKSPACE -DCMAKE_BUILD_TYPE=$BUILD_TYPE -G Ninja -DENABLE_LTO=False -DENABLE_ASSERTIONS=True -DENABLE_X86_HOST_DEBUG=True -DENABLE_INTERPRETER=True -DBUILD_FEX_LINUX_TESTS=True -DENABLE_GLIBC_ALLOCATOR_HOOK_FAULT=True -DENABLE_JEMALLOC_GLIBC_ALLOC=False -DCMAKE_INSTALL_PREFIX=${{runner.workspace}}/build/install
+
+    - name: Build
+      working-directory: ${{runner.workspace}}/build
+      shell: bash
+      # Execute the build.  You can specify a specific target with "--target <NAME>"
+      run: cmake --build . --config $BUILD_TYPE
+
+    - name: Install
+      working-directory: ${{runner.workspace}}/build
+      shell: bash
+      run: cmake --build . --config $BUILD_TYPE --target install
+
+    - name: ASM Tests
+      working-directory: ${{runner.workspace}}/build
+      shell: bash
+      # Execute the unit tests
+      run: cmake --build . --config $BUILD_TYPE --target asm_tests
+
+    - name: ASM Test Results move
+      if: ${{ always() }}
+      shell: bash
+      working-directory: ${{runner.workspace}}/build
+      run: mv ${{runner.workspace}}/build/Testing/Temporary/LastTest.log ${{runner.workspace}}/build/Testing/Temporary/LastTest_ASM.log || true
+
+    - name: IR Tests
+      working-directory: ${{runner.workspace}}/build
+      shell: bash
+      # Execute the unit tests
+      run: cmake --build . --config $BUILD_TYPE --target ir_tests
+
+    - name: IR Test Results move
+      if: ${{ always() }}
+      shell: bash
+      working-directory: ${{runner.workspace}}/build
+      run: mv ${{runner.workspace}}/build/Testing/Temporary/LastTest.log ${{runner.workspace}}/build/Testing/Temporary/LastTest_IR.log || true
+
+    - name: Posix Tests
+      working-directory: ${{runner.workspace}}/build
+      shell: bash
+      # Execute the posixtest
+      run: cmake --build . --config $BUILD_TYPE --target posix_tests
+
+    - name: Posix Test Results move
+      if: ${{ always() }}
+      shell: bash
+      working-directory: ${{runner.workspace}}/build
+      run: mv ${{runner.workspace}}/build/Testing/Temporary/LastTest.log ${{runner.workspace}}/build/Testing/Temporary/LastTest_Posix.log || true
+
+    - name: gcc target tests 64
+      working-directory: ${{runner.workspace}}/build
+      shell: bash
+      # Execute the gvisor tests
+      run: cmake --build . --config $BUILD_TYPE --target gcc_target_tests_64
+
+    - name: GCC64 Test Results move
+      if: ${{ always() }}
+      shell: bash
+      working-directory: ${{runner.workspace}}/build
+      run: mv ${{runner.workspace}}/build/Testing/Temporary/LastTest.log ${{runner.workspace}}/build/Testing/Temporary/LastTest_GCC64.log || true
+
+    - name: gcc target tests 32
+      working-directory: ${{runner.workspace}}/build
+      shell: bash
+      # Execute the gvisor tests
+      run: cmake --build . --config $BUILD_TYPE --target gcc_target_tests_32
+
+    - name: GCC32 Test Results move
+      if: ${{ always() }}
+      shell: bash
+      working-directory: ${{runner.workspace}}/build
+      run: mv ${{runner.workspace}}/build/Testing/Temporary/LastTest.log ${{runner.workspace}}/build/Testing/Temporary/LastTest_GCC32.log || true
+
+    - name: APITest tests
+      working-directory: ${{runner.workspace}}/build
+      shell: bash
+      run: cmake --build . --config $BUILD_TYPE --target api_tests
+
+    - name: APITest Test Results move
+      if: ${{ always() }}
+      shell: bash
+      working-directory: ${{runner.workspace}}/build
+      run: mv ${{runner.workspace}}/build/Testing/Temporary/LastTest.log ${{runner.workspace}}/build/Testing/Temporary/LastTest_APITests.log || true
+
+    - name: FEXCore APITest tests
+      working-directory: ${{runner.workspace}}/build
+      shell: bash
+      run: cmake --build . --config $BUILD_TYPE --target fexcore_apitests
+
+    - name: FEXCore APITest Test Results move
+      if: ${{ always() }}
+      shell: bash
+      working-directory: ${{runner.workspace}}/build
+      run: mv ${{runner.workspace}}/build/Testing/Temporary/LastTest.log ${{runner.workspace}}/build/Testing/Temporary/LastTest_FEXCoreAPITests.log || true
+
+    - name: FEXLinuxTests
+      working-directory: ${{runner.workspace}}/build
+      shell: bash
+      run: cmake --build . --config $BUILD_TYPE --target fex_linux_tests_all
+
+    - name: FEXLinuxTests Results move
+      if: ${{ always() }}
+      shell: bash
+      working-directory: ${{runner.workspace}}/build
+      run: mv ${{runner.workspace}}/build/Testing/Temporary/LastTest.log ${{runner.workspace}}/build/Testing/Temporary/LastTest_FEXLinuxTests.log || true
+
+    - name: Truncate test results
+      if: ${{ always() }}
+      shell: bash
+      working-directory: ${{runner.workspace}}/build
+      # Cap out the log files at 20M in case something crash spins and dumps fault text
+      # ASM tests get quite close to 10MB
+      run: truncate --size=<20M ${{runner.workspace}}/build/Testing/Temporary/LastTest_*.log || true
+
+    - name: Remove old SHM regions
+      if: ${{ always() }}
+      shell: bash
+      working-directory: ${{runner.workspace}}/build
+      run: cmake --build . --config $BUILD_TYPE --target remove_old_shm_regions
+
+    - name: Set runner name
+      if: ${{ always() }}
+      run: echo "runner_name=$(hostname)" >> $GITHUB_ENV
+
+    - name: Upload results
+      if: ${{ always() }}
+      uses: 'actions/upload-artifact@v3'
+      timeout-minutes: 1
+      with:
+        name: Results-${{ env.runner_name }}
+        path: ${{runner.workspace}}/build/Testing/Temporary/LastTest_*.log
+        retention-days: 3
+
@@ -0,0 +1,109 @@
+name: Instruction Count CI run
+
+on:
+  push:
+    branches:
+      - main
+  pull_request:
+    branches:
+      - main
+
+env:
+  # Customize the CMake build type here (Release, Debug, RelWithDebInfo, etc.)
+  BUILD_TYPE: Release
+  CC: clang
+  CXX: clang++
+  FEX_ENABLEAVX: 1
+
+jobs:
+  build:
+    runs-on: ${{ matrix.arch }}
+    strategy:
+      matrix:
+        arch: [[self-hosted, ARM64]]
+      fail-fast: false
+
+    steps:
+    - uses: actions/checkout@v3
+
+    - name: Set runner label
+      run: echo "runner_label=${{ matrix.arch[1] }}" >> $GITHUB_ENV
+
+    - name: Set rootfs paths
+      run: |
+        echo "FEX_ROOTFS_MOUNT=/mnt/AutoNFS/rootfs/" >> $GITHUB_ENV
+        echo "FEX_ROOTFS_PATH=$HOME/Rootfs/" >> $GITHUB_ENV
+        echo "FEX_ROOTFS=$HOME/Rootfs/" >> $GITHUB_ENV
+        echo "ROOTFS=$HOME/Rootfs/" >> $GITHUB_ENV
+
+    - name: Update RootFS cache
+      # Use a bash shell so we can use the same syntax for environment variable
+      # access regardless of the host operating system
+      shell: bash
+      run: $GITHUB_WORKSPACE/Scripts/CI_FetchRootFS.py
+
+    - name : submodule checkout
+      # Need to update submodules
+      run: |
+        git submodule sync --recursive
+        git submodule update --init --depth 1
+
+    - name: Clean Build Environment
+      run: rm -Rf ${{runner.workspace}}/build
+
+    - name: Create Build Environment
+      # Some projects don't allow in-source building, so create a separate build directory
+      # We'll use this as our working directory for all subsequent commands
+      run: cmake -E make_directory ${{runner.workspace}}/build
+
+    - name: Configure CMake
+      # Use a bash shell so we can use the same syntax for environment variable
+      # access regardless of the host operating system
+      shell: bash
+      working-directory: ${{runner.workspace}}/build
+      # Note the current convention is to use the -S and -B options here to specify source
+      # and build directories, but this is only available with CMake 3.13 and higher.
+      # The CMake binaries on the Github Actions machines are (as of this writing) 3.12
+      run: cmake $GITHUB_WORKSPACE -DCMAKE_BUILD_TYPE=$BUILD_TYPE -G Ninja -DENABLE_VIXL_SIMULATOR=False -DENABLE_VIXL_DISASSEMBLER=True -DENABLE_LTO=False -DENABLE_ASSERTIONS=True
+
+    - name: Build
+      working-directory: ${{runner.workspace}}/build
+      shell: bash
+      env:
+        FEX_DISABLETELEMETRY: 1
+      # Execute the build.  You can specify a specific target with "--target <NAME>"
+      run: cmake --build . --config $BUILD_TYPE --target CodeSizeValidation instcountci_test_files
+
+    - name: Instruction Count Tests
+      working-directory: ${{runner.workspace}}/build
+      shell: bash
+      # Execute the unit tests
+      run: cmake --build . --config $BUILD_TYPE --target instcountci_tests
+
+    - name: Instruction Count Test Results move
+      if: ${{ always() }}
+      shell: bash
+      working-directory: ${{runner.workspace}}/build
+      run: mv ${{runner.workspace}}/build/Testing/Temporary/LastTest.log ${{runner.workspace}}/build/Testing/Temporary/LastTest_InstCountCI.log || true
+
+    - name: Truncate test results
+      if: ${{ always() }}
+      shell: bash
+      working-directory: ${{runner.workspace}}/build
+      # Cap out the log files at 20M in case something crash spins and dumps fault text
+      # ASM tests get quite close to 10MB
+      run: truncate --size=<20M ${{runner.workspace}}/build/Testing/Temporary/LastTest_*.log || true
+
+    - name: Set runner name
+      if: ${{ always() }}
+      run: echo "runner_name=$(hostname)" >> $GITHUB_ENV
+
+    - name: Upload results
+      if: ${{ always() }}
+      uses: 'actions/upload-artifact@v3'
+      timeout-minutes: 1
+      with:
+        name: Results-${{ env.runner_name }}
+        path: ${{runner.workspace}}/build/Testing/Temporary/LastTest_*.log
+        retention-days: 3
+
@@ -0,0 +1,97 @@
+name: Mingw build
+
+on:
+  push:
+    branches:
+      - main
+  pull_request:
+    branches:
+      - main
+
+env:
+  BUILD_TYPE: Debug
+  FEX_ENABLEAVX: 1
+
+jobs:
+  build:
+    runs-on: ${{ matrix.arch }}
+    strategy:
+      matrix:
+        arch: [[self-hosted, x64, mingw], [self-hosted, ARM64, mingw]]
+      fail-fast: false
+
+    steps:
+    - uses: actions/checkout@v3
+
+    - name: Set runner label
+      run: echo "runner_label=${{ matrix.arch[1] }}" >> $GITHUB_ENV
+
+    - name: Add MingGW to PATH
+      run: echo "$HOME/llvm-mingw/build/bin/" >> $GITHUB_PATH
+
+    - name: Set CC x86
+      if: matrix.arch[1] == 'x64'
+      run: |
+        echo "MINGW_TRIPLE=x86_64-w64-mingw32" >> $GITHUB_ENV
+
+    - name: Set CC Arm64
+      if: matrix.arch[1] == 'ARM64'
+      run: |
+        echo "MINGW_TRIPLE=aarch64-w64-mingw32" >> $GITHUB_ENV
+
+    - name: Set rootfs paths
+      run: |
+        echo "FEX_ROOTFS_MOUNT=/mnt/AutoNFS/rootfs/" >> $GITHUB_ENV
+        echo "FEX_ROOTFS_PATH=$HOME/Rootfs/" >> $GITHUB_ENV
+        echo "FEX_ROOTFS=$HOME/Rootfs/" >> $GITHUB_ENV
+        echo "ROOTFS=$HOME/Rootfs/" >> $GITHUB_ENV
+
+    - name: Update RootFS cache
+      # Use a bash shell so we can use the same syntax for environment variable
+      # access regardless of the host operating system
+      shell: bash
+      run: $GITHUB_WORKSPACE/Scripts/CI_FetchRootFS.py
+
+    - name : submodule checkout
+      # Need to update submodules
+      run: |
+        git submodule sync --recursive
+        git submodule update --init --depth 1
+
+    - name: Clean Build Environment
+      run: rm -Rf ${{runner.workspace}}/build
+
+    - name: Create Build Environment
+      # Some projects don't allow in-source building, so create a separate build directory
+      # We'll use this as our working directory for all subsequent commands
+      run: cmake -E make_directory ${{runner.workspace}}/build
+
+    - name: Configure CMake
+      # Use a bash shell so we can use the same syntax for environment variable
+      # access regardless of the host operating system
+      shell: bash
+      working-directory: ${{runner.workspace}}/build
+      # Note the current convention is to use the -S and -B options here to specify source
+      # and build directories, but this is only available with CMake 3.13 and higher.
+      # The CMake binaries on the Github Actions machines are (as of this writing) 3.12
+      run: cmake $GITHUB_WORKSPACE -DCMAKE_BUILD_TYPE=$BUILD_TYPE -DCMAKE_TOOLCHAIN_FILE=$GITHUB_WORKSPACE/toolchain_mingw.cmake -DMINGW_TRIPLE=$MINGW_TRIPLE -G Ninja -DENABLE_LTO=False -DENABLE_ASSERTIONS=True -DENABLE_X86_HOST_DEBUG=True -DENABLE_INTERPRETER=False -DBUILD_TESTS=False -DENABLE_JEMALLOC=False -DENABLE_JEMALLOC_GLIBC_ALLOC=False -DCMAKE_INSTALL_PREFIX=${{runner.workspace}}/build/install
+
+    - name: Build
+      working-directory: ${{runner.workspace}}/build
+      shell: bash
+      # Execute the build.  You can specify a specific target with "--target <NAME>"
+      run: cmake --build . --config $BUILD_TYPE
+
+    - name: Set runner name
+      if: ${{ always() }}
+      run: echo "runner_name=$(hostname)" >> $GITHUB_ENV
+
+    - name: Upload results
+      if: ${{ always() }}
+      uses: 'actions/upload-artifact@v3'
+      timeout-minutes: 1
+      with:
+        name: Results-${{ env.runner_name }}
+        path: ${{runner.workspace}}/build/Testing/Temporary/LastTest_*.log
+        retention-days: 3
+
@@ -13,6 +13,7 @@ env:
  BUILD_TYPE: Release
  CC: clang
  CXX: clang++
+  FEX_ENABLEAVX: 1

 jobs:
  build:
@@ -24,7 +25,7 @@ jobs:
      fail-fast: false

    steps:
-    - uses: actions/checkout@v2
+    - uses: actions/checkout@v3

    - name: Set runner label
      run: echo "runner_label=${{ matrix.arch[1] }}" >> $GITHUB_ENV
@@ -64,7 +65,7 @@ jobs:
      # Note the current convention is to use the -S and -B options here to specify source
      # and build directories, but this is only available with CMake 3.13 and higher.
      # The CMake binaries on the Github Actions machines are (as of this writing) 3.12
-      run: cmake $GITHUB_WORKSPACE -DCMAKE_BUILD_TYPE=$BUILD_TYPE -G Ninja -DENABLE_VIXL_SIMULATOR=True -DENABLE_LTO=False -DENABLE_ASSERTIONS=True -DENABLE_X86_HOST_DEBUG=True
+      run: cmake $GITHUB_WORKSPACE -DCMAKE_BUILD_TYPE=$BUILD_TYPE -G Ninja -DENABLE_VIXL_SIMULATOR=True -DENABLE_VIXL_DISASSEMBLER=True -DENABLE_LTO=False -DENABLE_ASSERTIONS=True -DENABLE_X86_HOST_DEBUG=True

    - name: Build
      working-directory: ${{runner.workspace}}/build
@@ -84,6 +85,21 @@ jobs:
      working-directory: ${{runner.workspace}}/build
      run: mv ${{runner.workspace}}/build/Testing/Temporary/LastTest.log ${{runner.workspace}}/build/Testing/Temporary/LastTest_ASM.log || true

+    - name: ASM Tests 128-bit
+      working-directory: ${{runner.workspace}}/build
+      shell: bash
+      env:
+        FEX_HOSTFEATURES: "disableavx"
+        FEX_FORCESVEWIDTH: "128"
+      # Execute the unit tests
+      run: cmake --build . --config $BUILD_TYPE --target asm_tests
+
+    - name: ASM Test 128-bit Results move
+      if: ${{ always() }}
+      shell: bash
+      working-directory: ${{runner.workspace}}/build
+      run: mv ${{runner.workspace}}/build/Testing/Temporary/LastTest.log ${{runner.workspace}}/build/Testing/Temporary/LastTest_ASM128bit.log || true
+
    - name: IR Tests
      working-directory: ${{runner.workspace}}/build
      shell: bash
@@ -110,7 +126,8 @@ jobs:

    - name: Upload results
      if: ${{ always() }}
-      uses: 'actions/upload-artifact@v2'
+      uses: 'actions/upload-artifact@v3'
+      timeout-minutes: 1
      with:
        name: Results-${{ env.runner_name }}
        path: ${{runner.workspace}}/build/Testing/Temporary/LastTest_*.log
@@ -3,7 +3,7 @@
 	path = External/vixl
 	url = https://github.com/FEX-Emu/vixl.git
 [submodule "External/cpp-optparse"]
-	path = External/cpp-optparse
+	path = Source/Common/cpp-optparse
 	url = https://github.com/Sonicadvance1/cpp-optparse
 [submodule "External/imgui"]
 	path = External/imgui
@@ -48,8 +48,11 @@
 [submodule "External/robin-map"]
 	shallow = true
 	path = External/robin-map
-	url = https://github.com/Tessil/robin-map.git
+	url = https://github.com/FEX-Emu/robin-map.git
 [submodule "External/Vulkan-Headers"]
 	shallow = true
 	path = External/Vulkan-Headers
 	url = https://github.com/KhronosGroup/Vulkan-Headers.git
+[submodule "External/jemalloc_glibc"]
+	path = External/jemalloc_glibc
+	url = https://github.com/FEX-Emu/jemalloc.git
@@ -0,0 +1,30 @@
+# Extracts a version from the passed in version string in the form of "<Major>.<Minor>.<Patch>".
+# If a part of the version is missing then it gets set as zero.
+# Version variables returned in:
+# ${Package}_VERSION_MAJOR
+# ${Package}_VERSION_MINOR
+# ${Package}_VERSION_PATCH
+function(version_to_variables VERSION _Package)
+  string(REPLACE "." ";" VERSION_LIST "${VERSION}")
+  list (LENGTH VERSION_LIST VERSION_LEN)
+  if (${VERSION_LEN} GREATER 0)
+    list(GET VERSION_LIST 0 VERSION_MAJOR)
+    set(${_Package}_VERSION_MAJOR ${VERSION_MAJOR} PARENT_SCOPE)
+  else()
+    set(${_Package}_VERSION_MAJOR 0 PARENT_SCOPE)
+  endif()
+
+  if (${VERSION_LEN} GREATER 1)
+    list(GET VERSION_LIST 1 VERSION_MINOR)
+    set(${_Package}_VERSION_MINOR ${VERSION_MINOR} PARENT_SCOPE)
+  else()
+    set(${_Package}_VERSION_MINOR 0 PARENT_SCOPE)
+  endif()
+
+  if (${VERSION_LEN} GREATER 2)
+    list(GET VERSION_LIST 2 VERSION_PATCH)
+    set(${_Package}_VERSION_PATCH ${VERSION_PATCH} PARENT_SCOPE)
+  else()
+    set(${_Package}_VERSION_PATCH 0 PARENT_SCOPE)
+  endif()
+endfunction()
@@ -7,21 +7,21 @@ CHECK_INCLUDE_FILES ("gdb/jit-reader.h" HAVE_GDB_JIT_READER_H)
 option(BUILD_TESTS "Build unit tests to ensure sanity" TRUE)
 option(BUILD_FEX_LINUX_TESTS "Build FEXLinuxTests, requires x86 compiler" FALSE)
 option(BUILD_THUNKS "Build thunks" FALSE)
-option(BUILD_CLANG_THUNKS "Build thunks with clang" FALSE)
+option(BUILD_FEXCONFIG "Build FEXConfig, requires SDL2 and X11" TRUE)
+option(ENABLE_CLANG_THUNKS "Build thunks with clang" FALSE)
 option(ENABLE_CLANG_FORMAT "Run clang format over the source" FALSE)
 option(ENABLE_IWYU "Enables include what you use program" FALSE)
 option(ENABLE_LTO "Enable LTO with compilation" TRUE)
 option(ENABLE_XRAY "Enable building with LLVM X-Ray" FALSE)
-option(ENABLE_LLD "Enable linking with lld" FALSE)
-option(ENABLE_MOLD "Enable linking with mold" FALSE)
+set(USE_LINKER "" CACHE STRING "Allow overriding the linker path directly")
 option(ENABLE_ASAN "Enables Clang ASAN" FALSE)
 option(ENABLE_TSAN "Enables Clang TSAN" FALSE)
 option(ENABLE_ASSERTIONS "Enables assertions in build" FALSE)
 option(ENABLE_GDB_SYMBOLS "Enables GDBSymbols integration support" ${HAVE_GDB_JIT_READER_H})
-option(ENABLE_VISUAL_DEBUGGER "Enables the visual debugger for compiling" FALSE)
 option(ENABLE_STRICT_WERROR "Enables stricter -Werror for CI" FALSE)
 option(ENABLE_WERROR "Enables -Werror" FALSE)
 option(ENABLE_JEMALLOC "Enables jemalloc allocator" TRUE)
+option(ENABLE_JEMALLOC_GLIBC_ALLOC "Enables jemalloc glibc allocator" TRUE)
 option(ENABLE_OFFLINE_TELEMETRY "Enables FEX offline telemetry" TRUE)
 option(ENABLE_COMPILE_TIME_TRACE "Enables time trace compile option" FALSE)
 option(ENABLE_LIBCXX "Enables LLVM libc++" FALSE)
@@ -29,13 +29,23 @@ option(ENABLE_INTERPRETER "Enables FEX's Interpreter" FALSE)
 option(ENABLE_CCACHE "Enables ccache for compile caching" TRUE)
 option(ENABLE_TERMUX_BUILD "Forces building for Termux on a non-Termux build machine" FALSE)
 option(ENABLE_VIXL_SIMULATOR "Forces the FEX JIT to use the VIXL simulator" FALSE)
+option(ENABLE_VIXL_DISASSEMBLER "Enables debug disassembler output with VIXL" FALSE)
+option(COMPILE_VIXL_DISASSEMBLER "Compiles the vixl disassembler in to vixl" FALSE)
 option(ENABLE_FEXCORE_PROFILER "Enables use of the FEXCore timeline profiling capabilities" FALSE)
 set (FEXCORE_PROFILER_BACKEND "gpuvis" CACHE STRING "Set which backend you want to use for the FEXCore profiler")
+option(ENABLE_GLIBC_ALLOCATOR_HOOK_FAULT "Enables glibc memory allocation hooking with fault for CI testing")

 set (X86_32_TOOLCHAIN_FILE "${CMAKE_CURRENT_SOURCE_DIR}/toolchain_x86_32.cmake" CACHE FILEPATH "Toolchain file for the (cross-)compiler targeting i686")
 set (X86_64_TOOLCHAIN_FILE "${CMAKE_CURRENT_SOURCE_DIR}/toolchain_x86_64.cmake" CACHE FILEPATH "Toolchain file for the (cross-)compiler targeting x86_64")
 set (DATA_DIRECTORY "${CMAKE_INSTALL_PREFIX}/share/fex-emu" CACHE PATH "global data directory")

+string(FIND ${CMAKE_BASE_NAME} mingw CONTAINS_MINGW)
+if (NOT CONTAINS_MINGW EQUAL -1)
+  message (STATUS "Mingw build")
+  set (MINGW_BUILD TRUE)
+  set (ENABLE_JEMALLOC FALSE)
+endif()
+
 if (ENABLE_FEXCORE_PROFILER)
  add_definitions(-DENABLE_FEXCORE_PROFILER=1)
  string(TOUPPER "${FEXCORE_PROFILER_BACKEND}" FEXCORE_PROFILER_BACKEND)
@@ -47,6 +57,14 @@ if (ENABLE_FEXCORE_PROFILER)
  endif()
 endif()

+if (ENABLE_JEMALLOC_GLIBC_ALLOC AND ENABLE_GLIBC_ALLOCATOR_HOOK_FAULT)
+  message(FATAL_ERROR "Can't have both glibc fault allocator and jemalloc glibc allocator enabled at the same time")
+endif()
+
+if (ENABLE_GLIBC_ALLOCATOR_HOOK_FAULT)
+  add_definitions(-DGLIBC_ALLOCATOR_FAULT=1)
+endif()
+
 # uninstall target
 if(NOT TARGET uninstall)
  configure_file(
@@ -138,13 +156,9 @@ endif()

 set (PTHREAD_LIB pthread)

-if (ENABLE_LLD AND ENABLE_MOLD)
-  message (FATAL_ERROR "Cannot enable both lld and mold")
-elseif (ENABLE_LLD)
-  set (LD_OVERRIDE "-fuse-ld=lld")
-  add_link_options(${LD_OVERRIDE})
-elseif (ENABLE_MOLD)
-  add_link_options("-fuse-ld=mold")
+if (USE_LINKER)
+  message(STATUS "Overriding linker to: ${USE_LINKER}")
+  add_link_options("-fuse-ld=${USE_LINKER}")
 endif()

 if (ENABLE_LIBCXX)
@@ -161,8 +175,13 @@ endif()
 if(DEFINED ENV{TERMUX_VERSION} OR ENABLE_TERMUX_BUILD)
  add_definitions(-DTERMUX_BUILD=1)
  set(TERMUX_BUILD 1)
+
  # Termux doesn't support Jemalloc due to bad interactions between emutls, jemalloc, and scudo
  set(ENABLE_JEMALLOC FALSE)
+
+  # Termux builds can't rely on X11 packages
+  # SDL2 isn't even compiled with GL support so our GUIs wouldn't even work
+  set(BUILD_FEXCONFIG FALSE)
 endif()

 if (ENABLE_ASAN)
@@ -176,7 +195,22 @@ if (ENABLE_TSAN)
  link_libraries(-fno-omit-frame-pointer -fsanitize=thread)
 endif()

+if (ENABLE_JEMALLOC_GLIBC_ALLOC)
+  # The glibc jemalloc subproject which hooks the glibc allocator.
+  # Required for thunks to work.
+  # All host native libraries will use this allocator, while *most* other FEX internal allocations will use the other jemalloc allocator.
+  add_definitions(-DENABLE_JEMALLOC_GLIBC=1)
+  add_subdirectory(External/jemalloc_glibc/)
+else()
+  message (STATUS
+    " jemalloc glibc allocator disabled!\n"
+    " This is not a recommended configuration!\n"
+    " This will very explicitly break thunk execution!\n"
+    " Use at your own risk!")
+endif()
+
 if (ENABLE_JEMALLOC)
+  # The jemalloc subproject that all FEXCore fextl objects allocate through.
  add_definitions(-DENABLE_JEMALLOC=1)
  add_subdirectory(External/jemalloc/)
  include_directories(External/jemalloc/pregen/include/)
@@ -196,8 +230,13 @@ set (CMAKE_LINKER_FLAGS_RELEASE "${CMAKE_LINKER_FLAGS_RELEASE} -fomit-frame-poin

 include_directories(External/robin-map/include/)

+if (BUILD_TESTS)
+  # Enable vixl disassembler if tests are enabled.
+  set(COMPILE_VIXL_DISASSEMBLER TRUE)
+endif()
+
 add_subdirectory(External/vixl/)
-include_directories(External/vixl/src/)
+include_directories(SYSTEM External/vixl/src/)

 if (CMAKE_CXX_COMPILER_ID STREQUAL "GNU")
  # This means we were attempted to get compiled with GCC
@@ -223,9 +262,8 @@ if (BUILD_TESTS)
  include(Catch)
 endif()

-add_subdirectory(External/cpp-optparse/)
-include_directories(External/cpp-optparse/)
-
+# Disable fmt install
+set(FMT_INSTALL OFF)
 add_subdirectory(External/fmt/)

 add_subdirectory(External/imgui/)
@@ -389,7 +427,7 @@ if (BUILD_TESTS)
 endif()

 add_subdirectory(FEXHeaderUtils/)
-add_subdirectory(External/FEXCore)
+add_subdirectory(FEXCore/)

 # Binfmt_misc files must be installed prior to Source/ installs
 add_subdirectory(Data/binfmts/)
@@ -1,5 +0,0 @@
-{
-  "Config": {
-    "x86dec_SynchronizeRIPOnAllBlocks": "1"
-  }
-}
@@ -1,5 +0,0 @@
-{
-  "Config": {
-    "x86dec_SynchronizeRIPOnAllBlocks": "1"
-  }
-}
@@ -0,0 +1,5 @@
+{
+  "Config": {
+    "HideHypervisorBit": "1"
+  }
+}
@@ -1,5 +0,0 @@
-{
-  "Config": {
-    "x86dec_SynchronizeRIPOnAllBlocks": "1"
-  }
-}
@@ -1,5 +0,0 @@
-{
-  "Config": {
-    "x86dec_SynchronizeRIPOnAllBlocks": "1"
-  }
-}
@@ -6,10 +6,10 @@
        "X11"
      ],
      "Overlay": [
-        "@PREFIX_LIB@/x86_64-linux-gnu/libGL.so",
-        "@PREFIX_LIB@/x86_64-linux-gnu/libGL.so.1",
-        "@PREFIX_LIB@/x86_64-linux-gnu/libGL.so.1.2.0",
-        "@PREFIX_LIB@/x86_64-linux-gnu/libGL.so.1.7.0"
+        "@PREFIX_LIB@/libGL.so",
+        "@PREFIX_LIB@/libGL.so.1",
+        "@PREFIX_LIB@/libGL.so.1.2.0",
+        "@PREFIX_LIB@/libGL.so.1.7.0"
      ]
    },
    "GLESv2": {
@@ -18,17 +18,17 @@
        "X11"
      ],
      "Overlay": [
-        "@PREFIX_LIB@/x86_64-linux-gnu/libGLESv2.so",
-        "@PREFIX_LIB@/x86_64-linux-gnu/libGLESv2.so.2",
-        "@PREFIX_LIB@/x86_64-linux-gnu/libGLESv2.so.2.0.0"
+        "@PREFIX_LIB@/libGLESv2.so",
+        "@PREFIX_LIB@/libGLESv2.so.2",
+        "@PREFIX_LIB@/libGLESv2.so.2.0.0"
      ]
    },
    "X11": {
      "Library": "libX11-guest.so",
      "Overlay": [
-        "@PREFIX_LIB@/x86_64-linux-gnu/libX11.so",
-        "@PREFIX_LIB@/x86_64-linux-gnu/libX11.so.6",
-        "@PREFIX_LIB@/x86_64-linux-gnu/libX11.so.6.4.0"
+        "@PREFIX_LIB@/libX11.so",
+        "@PREFIX_LIB@/libX11.so.6",
+        "@PREFIX_LIB@/libX11.so.6.4.0"
      ]
    },
    "Vulkan": {
@@ -37,8 +37,8 @@
        "xcb"
      ],
      "Overlay": [
-        "@PREFIX_LIB@/x86_64-linux-gnu/libvulkan.so",
-        "@PREFIX_LIB@/x86_64-linux-gnu/libvulkan.so.1",
+        "@PREFIX_LIB@/libvulkan.so",
+        "@PREFIX_LIB@/libvulkan.so.1",
        "@HOME@/.local/share/Steam/ubuntu12_32/steam-runtime/pinned_libs_64/libvulkan.so.1"
      ],
      "Comment": [
@@ -46,131 +46,142 @@
      ]
    },
    "xcb": {
+      "Depends": [
+        "X11"
+      ],
      "Library": "libxcb-guest.so",
      "Overlay": [
-        "@PREFIX_LIB@/x86_64-linux-gnu/libxcb.so",
-        "@PREFIX_LIB@/x86_64-linux-gnu/libxcb.so.1",
-        "@PREFIX_LIB@/x86_64-linux-gnu/libxcb.so.1.1.0"
+        "@PREFIX_LIB@/libxcb.so",
+        "@PREFIX_LIB@/libxcb.so.1",
+        "@PREFIX_LIB@/libxcb.so.1.1.0"
      ]
    },
    "xcb-dri2": {
-      "Library": "libxcb_dri2-guest.so",
+      "Library": "libxcb-dri2-guest.so",
      "Overlay": [
-        "@PREFIX_LIB@/x86_64-linux-gnu/libxcb-dri2.so",
-        "@PREFIX_LIB@/x86_64-linux-gnu/libxcb-dri2.so.0",
-        "@PREFIX_LIB@/x86_64-linux-gnu/libxcb-dri2.so.0.0.0"
+        "@PREFIX_LIB@/libxcb-dri2.so",
+        "@PREFIX_LIB@/libxcb-dri2.so.0",
+        "@PREFIX_LIB@/libxcb-dri2.so.0.0.0"
      ]
    },
    "xcb-dri3": {
-      "Library": "libxcb_dri3-guest.so",
+      "Library": "libxcb-dri3-guest.so",
      "Overlay": [
-        "@PREFIX_LIB@/x86_64-linux-gnu/libxcb-dri3.so",
-        "@PREFIX_LIB@/x86_64-linux-gnu/libxcb-dri3.so.0",
-        "@PREFIX_LIB@/x86_64-linux-gnu/libxcb-dri3.so.0.0.0"
+        "@PREFIX_LIB@/libxcb-dri3.so",
+        "@PREFIX_LIB@/libxcb-dri3.so.0",
+        "@PREFIX_LIB@/libxcb-dri3.so.0.0.0"
      ]
    },
    "xcb-xfixes": {
-      "Library": "libxcb_xfixes-guest.so",
+      "Library": "libxcb-xfixes-guest.so",
      "Overlay": [
-        "@PREFIX_LIB@/x86_64-linux-gnu/libxcb-xfixes.so",
-        "@PREFIX_LIB@/x86_64-linux-gnu/libxcb-xfixes.so.0",
-        "@PREFIX_LIB@/x86_64-linux-gnu/libxcb-xfixes.so.0.0.0"
+        "@PREFIX_LIB@/libxcb-xfixes.so",
+        "@PREFIX_LIB@/libxcb-xfixes.so.0",
+        "@PREFIX_LIB@/libxcb-xfixes.so.0.0.0"
      ]
    },
    "xcb-shm": {
-      "Library": "libxcb_shm-guest.so",
+      "Library": "libxcb-shm-guest.so",
      "Overlay": [
-        "@PREFIX_LIB@/x86_64-linux-gnu/libxcb-shm.so",
-        "@PREFIX_LIB@/x86_64-linux-gnu/libxcb-shm.so.0",
-        "@PREFIX_LIB@/x86_64-linux-gnu/libxcb-shm.so.0.0.0"
+        "@PREFIX_LIB@/libxcb-shm.so",
+        "@PREFIX_LIB@/libxcb-shm.so.0",
+        "@PREFIX_LIB@/libxcb-shm.so.0.0.0"
      ]
    },
    "xcb-sync": {
-      "Library": "libxcb_sync-guest.so",
+      "Library": "libxcb-sync-guest.so",
      "Overlay": [
-        "@PREFIX_LIB@/x86_64-linux-gnu/libxcb-sync.so",
-        "@PREFIX_LIB@/x86_64-linux-gnu/libxcb-sync.so.1",
-        "@PREFIX_LIB@/x86_64-linux-gnu/libxcb-sync.so.1.0.0"
+        "@PREFIX_LIB@/libxcb-sync.so",
+        "@PREFIX_LIB@/libxcb-sync.so.1",
+        "@PREFIX_LIB@/libxcb-sync.so.1.0.0"
      ]
    },
    "xcb-randr": {
-      "Library": "libxcb_randr-guest.so",
+      "Library": "libxcb-randr-guest.so",
      "Overlay": [
-        "@PREFIX_LIB@/x86_64-linux-gnu/libxcb-randr.so",
-        "@PREFIX_LIB@/x86_64-linux-gnu/libxcb-randr.so.0",
-        "@PREFIX_LIB@/x86_64-linux-gnu/libxcb-randr.so.0.1.0"
+        "@PREFIX_LIB@/libxcb-randr.so",
+        "@PREFIX_LIB@/libxcb-randr.so.0",
+        "@PREFIX_LIB@/libxcb-randr.so.0.1.0"
      ]
    },
    "xcb-present": {
-      "Library": "libxcb_present-guest.so",
+      "Library": "libxcb-present-guest.so",
      "Overlay": [
-        "@PREFIX_LIB@/x86_64-linux-gnu/libxcb-present.so",
-        "@PREFIX_LIB@/x86_64-linux-gnu/libxcb-present.so.0",
-        "@PREFIX_LIB@/x86_64-linux-gnu/libxcb-present.so.0.0.0"
+        "@PREFIX_LIB@/libxcb-present.so",
+        "@PREFIX_LIB@/libxcb-present.so.0",
+        "@PREFIX_LIB@/libxcb-present.so.0.0.0"
      ]
    },
    "xcb-glx": {
-      "Library": "libxcb_glx-guest.so",
+      "Library": "libxcb-glx-guest.so",
      "Overlay": [
-        "@PREFIX_LIB@/x86_64-linux-gnu/libxcb-glx.so",
-        "@PREFIX_LIB@/x86_64-linux-gnu/libxcb-glx.so.0",
-        "@PREFIX_LIB@/x86_64-linux-gnu/libxcb-glx.so.0.0.0"
+        "@PREFIX_LIB@/libxcb-glx.so",
+        "@PREFIX_LIB@/libxcb-glx.so.0",
+        "@PREFIX_LIB@/libxcb-glx.so.0.0.0"
      ]
    },
    "xshmfence": {
-      "Library": "libshmfence-guest.so",
+      "Library": "libxshmfence-guest.so",
      "Overlay": [
-        "@PREFIX_LIB@/x86_64-linux-gnu/libxshmfence.so",
-        "@PREFIX_LIB@/x86_64-linux-gnu/libxshmfence.so.1",
-        "@PREFIX_LIB@/x86_64-linux-gnu/libxshmfence.so.1.0.0"
+        "@PREFIX_LIB@/libxshmfence.so",
+        "@PREFIX_LIB@/libxshmfence.so.1",
+        "@PREFIX_LIB@/libxshmfence.so.1.0.0"
      ]
    },
    "drm": {
      "Library": "libdrm-guest.so",
      "Overlay": [
-        "@PREFIX_LIB@/x86_64-linux-gnu/libdrm.so",
-        "@PREFIX_LIB@/x86_64-linux-gnu/libdrm.so.2",
-        "@PREFIX_LIB@/x86_64-linux-gnu/libdrm.so.2.4.0"
+        "@PREFIX_LIB@/libdrm.so",
+        "@PREFIX_LIB@/libdrm.so.2",
+        "@PREFIX_LIB@/libdrm.so.2.4.0"
      ]
    },
    "asound": {
      "Library": "libasound-guest.so",
      "Overlay": [
-        "@PREFIX_LIB@/x86_64-linux-gnu/libasound.so",
-        "@PREFIX_LIB@/x86_64-linux-gnu/libasound.so.2",
-        "@PREFIX_LIB@/x86_64-linux-gnu/libasound.so.2.0.0"
+        "@PREFIX_LIB@/libasound.so",
+        "@PREFIX_LIB@/libasound.so.2",
+        "@PREFIX_LIB@/libasound.so.2.0.0"
      ]
    },
    "Xrender": {
      "Library": "libXrender-guest.so",
      "Overlay": [
-        "@PREFIX_LIB@/x86_64-linux-gnu/libXrender.so",
-        "@PREFIX_LIB@/x86_64-linux-gnu/libXrender.so.1",
-        "@PREFIX_LIB@/x86_64-linux-gnu/libXrender.so.1.3.0"
+        "@PREFIX_LIB@/libXrender.so",
+        "@PREFIX_LIB@/libXrender.so.1",
+        "@PREFIX_LIB@/libXrender.so.1.3.0"
      ]
    },
    "Xext": {
      "Library": "libXext-guest.so",
      "Overlay": [
-        "@PREFIX_LIB@/x86_64-linux-gnu/libXext.so",
-        "@PREFIX_LIB@/x86_64-linux-gnu/libXext.so.6",
-        "@PREFIX_LIB@/x86_64-linux-gnu/libXext.so.6.4.0"
+        "@PREFIX_LIB@/libXext.so",
+        "@PREFIX_LIB@/libXext.so.6",
+        "@PREFIX_LIB@/libXext.so.6.4.0"
      ]
    },
    "Xfixes": {
      "Library": "libXfixes-guest.so",
      "Overlay": [
-        "@PREFIX_LIB@/x86_64-linux-gnu/libXfixes.so",
-        "@PREFIX_LIB@/x86_64-linux-gnu/libXfixes.so.3",
-        "@PREFIX_LIB@/x86_64-linux-gnu/libXfixes.so.3.1.0"
+        "@PREFIX_LIB@/libXfixes.so",
+        "@PREFIX_LIB@/libXfixes.so.3",
+        "@PREFIX_LIB@/libXfixes.so.3.1.0"
      ]
    },
    "OpenCL": {
      "Library" : "libOpenCL-guest.so",
      "Overlay": [
-        "@PREFIX_LIB@/x86_64-linux-gnu/libOpenCL.so",
-        "@PREFIX_LIB@/x86_64-linux-gnu/libOpenCL.so.1",
-        "@PREFIX_LIB@/x86_64-linux-gnu/libOpenCL.so.1.0.0"
+        "@PREFIX_LIB@/libOpenCL.so",
+        "@PREFIX_LIB@/libOpenCL.so.1",
+        "@PREFIX_LIB@/libOpenCL.so.1.0.0"
+      ]
+    },
+    "WaylandClient": {
+      "Library" : "libwayland-client-guest.so",
+      "Overlay": [
+        "@PREFIX_LIB@/libwayland-client.so",
+        "@PREFIX_LIB@/libwayland-client.so.0",
+        "@PREFIX_LIB@/libwayland-client.so.0.20.0"
      ]
    },
    "":{}
@@ -6,3 +6,4 @@ mask \xff\xff\xff\xff\xff\xfe\xfe\x00\x00\x00\x00\xff\xff\xff\xff\xff\xfe\xff\xf
 credentials yes
 fix_binary yes
 preserve yes
+expose_interpreter optional
@@ -6,3 +6,4 @@ mask \xff\xff\xff\xff\xff\xfe\xfe\x00\x00\x00\x00\xff\xff\xff\xff\xff\xfe\xff\xf
 credentials yes
 fix_binary yes
 preserve yes
+expose_interpreter optional
@@ -1,64 +0,0 @@
-#include "Common/JitSymbols.h"
-
-#include <string>
-#include <unistd.h>
-
-#include <fmt/format.h>
-
-namespace FEXCore {
-  JITSymbols::JITSymbols() : fp{nullptr, std::fclose} {
-  }
-
-  JITSymbols::~JITSymbols() = default;
-
-  void JITSymbols::InitFile() {
-    const auto PerfMap = fmt::format("/tmp/perf-{}.map", getpid());
-
-    fp.reset(fopen(PerfMap.c_str(), "wb"));
-    if (fp) {
-      // Disable buffering on this file
-      setvbuf(fp.get(), nullptr, _IONBF, 0);
-    }
-  }
-
-  void JITSymbols::Register(const void *HostAddr, uint64_t GuestAddr, uint32_t CodeSize) {
-    if (!fp) return;
-
-    // Linux perf format is very straightforward
-    // `<HostPtr> <Size> <Name>\n`
-    fmt::print(fp.get(), "{} {:x} JIT_0x{:x}_{}\n", HostAddr, CodeSize, GuestAddr, HostAddr);
-  }
-
-  void JITSymbols::Register(const void *HostAddr, uint32_t CodeSize, std::string_view Name) {
-    if (!fp) return;
-
-    // Linux perf format is very straightforward
-    // `<HostPtr> <Size> <Name>\n`
-    fmt::print(fp.get(), "{} {:x} {}_{}\n", HostAddr, CodeSize, Name, HostAddr);
-  }
-
-  void JITSymbols::Register(const void *HostAddr, uint32_t CodeSize, std::string_view Name, uintptr_t Offset) {
-    if (!fp) return;
-
-    // Linux perf format is very straightforward
-    // `<HostPtr> <Size> <Name>\n`
-    fmt::print(fp.get(), "{} {:x} {}+0x{:x} ({})\n", HostAddr, CodeSize, Name, Offset, HostAddr);
-  }
-
-  void JITSymbols::RegisterNamedRegion(const void *HostAddr, uint32_t CodeSize, std::string_view Name) {
-    if (!fp) return;
-
-    // Linux perf format is very straightforward
-    // `<HostPtr> <Size> <Name>\n`
-    fmt::print(fp.get(), "{} {:x} {}\n", HostAddr, CodeSize, Name);
-  }
-
-  void JITSymbols::RegisterJITSpace(const void *HostAddr, uint32_t CodeSize) {
-    if (!fp) return;
-
-    // Linux perf format is very straightforward
-    // `<HostPtr> <Size> <Name>\n`
-    fmt::print(fp.get(), "{} {:x} FEXJIT\n", HostAddr, CodeSize);
-  }
-
-} // namespace FEXCore
@@ -1,91 +0,0 @@
-#include "Common/Paths.h"
-#include <FEXCore/Utils/LogManager.h>
-
-#include <cstdlib>
-#include <filesystem>
-#include <memory>
-#include <pwd.h>
-#include <system_error>
-#include <unistd.h>
-
-namespace FEXCore::Paths {
-  std::unique_ptr<std::string> CachePath;
-  std::unique_ptr<std::string> EntryCache;
-
-  char const* FindUserHomeThroughUID() {
-    auto passwd = getpwuid(geteuid());
-    if (passwd) {
-      return passwd->pw_dir;
-    }
-    return nullptr;
-  }
-
-  const char *GetHomeDirectory() {
-    char const *HomeDir = getenv("HOME");
-
-    // Try to get home directory from uid
-    if (!HomeDir) {
-      HomeDir = FindUserHomeThroughUID();
-    }
-
-    // try the PWD
-    if (!HomeDir) {
-      HomeDir = getenv("PWD");
-    }
-
-    // Still doesn't exit? You get local
-    if (!HomeDir) {
-      HomeDir = ".";
-    }
-
-    return HomeDir;
-  }
-
-  void InitializePaths() {
-    CachePath = std::make_unique<std::string>();
-    EntryCache = std::make_unique<std::string>();
-
-    char const *HomeDir = getenv("HOME");
-
-    if (!HomeDir) {
-      HomeDir = getenv("PWD");
-    }
-
-    if (!HomeDir) {
-      HomeDir = ".";
-    }
-
-    char *XDGDataDir = getenv("XDG_DATA_DIR");
-    if (XDGDataDir) {
-      *CachePath = XDGDataDir;
-    }
-    else {
-      if (HomeDir) {
-        *CachePath = HomeDir;
-      }
-    }
-
-    *CachePath += "/.fex-emu/";
-    *EntryCache = *CachePath + "/EntryCache/";
-
-    std::error_code ec{};
-    // Ensure the folder structure is created for our Data
-    if (!std::filesystem::exists(*EntryCache, ec) &&
-        !std::filesystem::create_directories(*EntryCache, ec)) {
-      LogMan::Msg::DFmt("Couldn't create EntryCache directory: '{}'", *EntryCache);
-    }
-  }
-
-  void ShutdownPaths() {
-    CachePath.reset();
-    EntryCache.reset();
-  }
-
-  std::string GetCachePath() {
-    return *CachePath;
-  }
-
-  std::string GetEntryCachePath() {
-    return *EntryCache;
-  }
-}
@@ -1,12 +0,0 @@
-#pragma once
-#include <string>
-
-namespace FEXCore::Paths {
-  void InitializePaths();
-  void ShutdownPaths();
-
-  const char *GetHomeDirectory();
-
-  std::string GetCachePath();
-  std::string GetEntryCachePath();
-}
@@ -1,29 +0,0 @@
-#pragma once
-#include <string>
-
-namespace FEXCore::StringUtils {
-  // Trim the left side of the string of whitespace and new lines
-  [[maybe_unused]] static std::string LeftTrim(std::string String, std::string TrimTokens = " \t\n\r") {
-    size_t pos = std::string::npos;
-    if ((pos = String.find_first_not_of(TrimTokens)) != std::string::npos) {
-      String.erase(0, pos);
-    }
-
-    return String;
-  }
-
-  // Trim the right side of the string of whitespace and new lines
-  [[maybe_unused]] static std::string RightTrim(std::string String, std::string TrimTokens = " \t\n\r") {
-    size_t pos = std::string::npos;
-    if ((pos = String.find_last_not_of(TrimTokens)) != std::string::npos) {
-      String.erase(String.begin() + pos + 1, String.end());
-    }
-
-    return String;
-  }
-
-  // Trim both the left and right of the string of whitespace and new lines
-  [[maybe_unused]] static std::string Trim(std::string String, std::string TrimTokens = " \t\n\r") {
-    return RightTrim(LeftTrim(String, TrimTokens), TrimTokens);
-  }
-}
@@ -1,239 +0,0 @@
-#include "Common/Paths.h"
-#include "Interface/Context/Context.h"
-#include "Interface/Core/Core.h"
-#include "Interface/Core/OpcodeDispatcher.h"
-#include "Interface/Core/X86Tables/X86Tables.h"
-
-#include <FEXCore/Core/CoreState.h>
-#include <FEXCore/Core/Context.h>
-#include <FEXCore/Core/CPUID.h>
-#include <FEXCore/Core/SignalDelegator.h>
-#include "FEXCore/Debug/InternalThreadState.h"
-
-#include <string.h>
-#include <utility>
-
-namespace FEXCore::HLE {
-  class SyscallVisitor;
-}
-
-namespace FEXCore::Context {
-  void InitializeStaticTables(OperatingMode Mode) {
-    FEXCore::Paths::InitializePaths();
-    X86Tables::InitializeInfoTables(Mode);
-    IR::InstallOpcodeHandlers(Mode);
-  }
-
-  void ShutdownStaticTables() {
-    FEXCore::Paths::ShutdownPaths();
-  }
-
-  FEXCore::Context::Context *CreateNewContext() {
-    return new FEXCore::Context::Context{};
-  }
-
-  bool InitializeContext(FEXCore::Context::Context *CTX) {
-    return FEXCore::CPU::CreateCPUCore(CTX);
-  }
-
-  void DestroyContext(FEXCore::Context::Context *CTX) {
-    if (CTX->ParentThread) {
-      CTX->DestroyThread(CTX->ParentThread);
-    }
-    delete CTX;
-  }
-
-  FEXCore::Core::InternalThreadState* InitCore(FEXCore::Context::Context *CTX, uint64_t InitialRIP, uint64_t StackPointer) {
-    return CTX->InitCore(InitialRIP, StackPointer);
-  }
-
-  void SetExitHandler(FEXCore::Context::Context *CTX, ExitHandler handler) {
-    CTX->CustomExitHandler = std::move(handler);
-  }
-
-  ExitHandler GetExitHandler(const FEXCore::Context::Context *CTX) {
-    return CTX->CustomExitHandler;
-  }
-
-  void Run(FEXCore::Context::Context *CTX) {
-    CTX->Run();
-  }
-
-  void Step(FEXCore::Context::Context *CTX) {
-    CTX->Step();
-  }
-
-  void CompileRIP(FEXCore::Core::InternalThreadState *Thread, uint64_t GuestRIP) {
-    Thread->CTX->CompileBlock(Thread->CurrentFrame, GuestRIP);
-  }
-
-  FEXCore::Context::ExitReason RunUntilExit(FEXCore::Context::Context *CTX) {
-    return CTX->RunUntilExit();
-  }
-
-  int GetProgramStatus(const FEXCore::Context::Context *CTX) {
-    return CTX->GetProgramStatus();
-  }
-
-  FEXCore::Context::ExitReason GetExitReason(const FEXCore::Context::Context *CTX) {
-    return CTX->ParentThread->ExitReason;
-  }
-
-  bool IsDone(const FEXCore::Context::Context *CTX) {
-    return CTX->IsPaused();
-  }
-
-  void GetCPUState(const FEXCore::Context::Context *CTX, FEXCore::Core::CPUState *State) {
-    memcpy(State, CTX->ParentThread->CurrentFrame, sizeof(FEXCore::Core::CPUState));
-  }
-
-  void SetCPUState(FEXCore::Context::Context *CTX, const FEXCore::Core::CPUState *State) {
-    memcpy(CTX->ParentThread->CurrentFrame, State, sizeof(FEXCore::Core::CPUState));
-  }
-
-  void Pause(FEXCore::Context::Context *CTX) {
-    CTX->Pause();
-  }
-
-  void Stop(FEXCore::Context::Context *CTX) {
-    CTX->Stop(false);
-  }
-
-  void SetCustomCPUBackendFactory(FEXCore::Context::Context *CTX, CustomCPUFactoryType Factory) {
-    CTX->CustomCPUFactory = std::move(Factory);
-  }
-
-  bool AddVirtualMemoryMapping([[maybe_unused]] FEXCore::Context::Context *CTX, [[maybe_unused]] uint64_t VirtualAddress, [[maybe_unused]] uint64_t PhysicalAddress, [[maybe_unused]] uint64_t Size) {
-    return false;
-  }
-
-  void RegisterExternalSyscallVisitor(FEXCore::Context::Context *CTX, [[maybe_unused]] uint64_t Syscall, [[maybe_unused]] FEXCore::HLE::SyscallVisitor *Visitor) {
-  }
-
-  HostFeatures GetHostFeatures(const FEXCore::Context::Context *CTX) {
-    return CTX->HostFeatures;
-  }
-
-  void HandleCallback(FEXCore::Context::Context *CTX, FEXCore::Core::InternalThreadState *Thread, uint64_t RIP) {
-    CTX->HandleCallback(Thread, RIP);
-  }
-
-  void RegisterHostSignalHandler(FEXCore::Context::Context *CTX, int Signal, HostSignalDelegatorFunction Func, bool Required) {
-      CTX->RegisterHostSignalHandler(Signal, std::move(Func), Required);
-  }
-
-  void RegisterFrontendHostSignalHandler(FEXCore::Context::Context *CTX, int Signal, HostSignalDelegatorFunction Func, bool Required) {
-    CTX->RegisterFrontendHostSignalHandler(Signal, std::move(Func), Required);
-  }
-
-  FEXCore::Core::InternalThreadState* CreateThread(FEXCore::Context::Context *CTX, FEXCore::Core::CPUState *NewThreadState, uint64_t ParentTID) {
-    return CTX->CreateThread(NewThreadState, ParentTID);
-  }
-
-  void ExecutionThread(FEXCore::Context::Context *CTX, FEXCore::Core::InternalThreadState *Thread) {
-    return CTX->ExecutionThread(Thread);
-  }
-
-  void InitializeThread(FEXCore::Context::Context *CTX, FEXCore::Core::InternalThreadState *Thread) {
-    return CTX->InitializeThread(Thread);
-  }
-
-  void RunThread(FEXCore::Context::Context *CTX, FEXCore::Core::InternalThreadState *Thread) {
-    CTX->RunThread(Thread);
-  }
-
-  void StopThread(FEXCore::Context::Context *CTX, FEXCore::Core::InternalThreadState *Thread) {
-    CTX->StopThread(Thread);
-  }
-
-  void DestroyThread(FEXCore::Context::Context *CTX, FEXCore::Core::InternalThreadState *Thread) {
-    CTX->DestroyThread(Thread);
-  }
-
-  void CleanupAfterFork(FEXCore::Context::Context *CTX, FEXCore::Core::InternalThreadState *Thread) {
-    CTX->CleanupAfterFork(Thread);
-  }
-  
-  void SetSignalDelegator(FEXCore::Context::Context *CTX, FEXCore::SignalDelegator *SignalDelegation) {
-    CTX->SignalDelegation = SignalDelegation;
-  }
-
-  void SetSyscallHandler(FEXCore::Context::Context *CTX, FEXCore::HLE::SyscallHandler *Handler) {
-    CTX->SyscallHandler = Handler;
-    CTX->SourcecodeResolver = Handler->GetSourcecodeResolver();
-  }
-
-  FEXCore::CPUID::FunctionResults RunCPUIDFunction(FEXCore::Context::Context *CTX, uint32_t Function, uint32_t Leaf) {
-    return CTX->CPUID.RunFunction(Function, Leaf);
-  }
-
-  FEX_DEFAULT_VISIBILITY FEXCore::CPUID::FunctionResults RunCPUIDFunctionName(FEXCore::Context::Context *CTX, uint32_t Function, uint32_t Leaf, uint32_t CPU) {
-    return CTX->CPUID.RunFunctionName(Function, Leaf, CPU);
-  }
-
-  void SetAOTIRLoader(FEXCore::Context::Context *CTX, std::function<int(const std::string&)> CacheReader) {
-    CTX->SetAOTIRLoader(CacheReader);
-  }
-
-  void SetAOTIRWriter(FEXCore::Context::Context *CTX, std::function<std::unique_ptr<std::ofstream>(const std::string&)> CacheWriter) {
-    CTX->SetAOTIRWriter(CacheWriter);
-  }
-
-  void SetAOTIRRenamer(FEXCore::Context::Context *CTX, std::function<void(const std::string&)> CacheRenamer) {
-    CTX->SetAOTIRRenamer(CacheRenamer);
-  }
-
-  void FinalizeAOTIRCache(FEXCore::Context::Context *CTX) {
-    CTX->FinalizeAOTIRCache();
-  }
-
-  void WriteFilesWithCode(FEXCore::Context::Context *CTX, std::function<void(const std::string& fileid, const std::string& filename)> Writer) {
-    CTX->WriteFilesWithCode(Writer);
-  }
-
-  IR::AOTIRCacheEntry *LoadAOTIRCacheEntry(FEXCore::Context::Context *CTX, const std::string &Name) {
-    return CTX->LoadAOTIRCacheEntry(Name);
-  }
-  void UnloadAOTIRCacheEntry(FEXCore::Context::Context *CTX, IR::AOTIRCacheEntry *Entry) {
-    return CTX->UnloadAOTIRCacheEntry(Entry);
-  }
-
-  CustomIRResult AddCustomIREntrypoint(FEXCore::Context::Context *CTX, uintptr_t Entrypoint, std::function<void(uintptr_t Entrypoint, FEXCore::IR::IREmitter *)> Handler, void *Creator, void *Data) {
-    return CTX->AddCustomIREntrypoint(Entrypoint, Handler, Creator, Data);
-  }
-
-  void AppendThunkDefinitions(FEXCore::Context::Context *CTX, std::vector<FEXCore::IR::ThunkDefinition> const& Definitions) {
-    CTX->AppendThunkDefinitions(Definitions);
-  }
-
-namespace Debug {
-  void CompileRIP(FEXCore::Context::Context *CTX, uint64_t RIP) {
-    CTX->CompileRIP(CTX->ParentThread, RIP);
-  }
-  uint64_t GetThreadCount(FEXCore::Context::Context *CTX) {
-    return CTX->GetThreadCount();
-  }
-
-  FEXCore::Core::RuntimeStats *GetRuntimeStatsForThread(FEXCore::Context::Context *CTX, uint64_t Thread) {
-    return CTX->GetRuntimeStatsForThread(Thread);
-  }
-
-  bool GetDebugDataForRIP(FEXCore::Context::Context *CTX, uint64_t RIP, FEXCore::Core::DebugData *Data) {
-    return CTX->GetDebugDataForRIP(RIP, Data);
-  }
-
-  bool FindHostCodeForRIP(FEXCore::Context::Context *CTX, uint64_t RIP, uint8_t **Code) {
-    return CTX->FindHostCodeForRIP(RIP, Code);
-  }
-
-  // XXX:
-  // bool FindIRForRIP(FEXCore::Context::Context *CTX, uint64_t RIP, FEXCore::IR::IntrusiveIRList **ir) {
-  //   return CTX->FindIRForRIP(RIP, ir);
-  // }
-
-  // void SetIRForRIP(FEXCore::Context::Context *CTX, uint64_t RIP, FEXCore::IR::IntrusiveIRList *const ir) {
-  //   CTX->SetIRForRIP(RIP, ir);
-  // }
-}
-
-}
@@ -1,381 +0,0 @@
-#pragma once
-
-#include "Common/JitSymbols.h"
-#include "FEXHeaderUtils/ScopedSignalMask.h"
-#include "Interface/Core/CPUID.h"
-#include "Interface/Core/X86HelperGen.h"
-#include "Interface/Core/ObjectCache/ObjectCacheService.h"
-#include "Interface/Core/Dispatcher/Dispatcher.h"
-#include "Interface/IR/AOTIR.h"
-#include <FEXCore/Config/Config.h>
-#include <FEXCore/Core/Context.h>
-#include <FEXCore/Core/CoreState.h>
-#include <FEXCore/Core/HostFeatures.h>
-#include <FEXCore/Core/SignalDelegator.h>
-#include <FEXCore/Debug/InternalThreadState.h>
-#include <FEXCore/Utils/CompilerDefs.h>
-#include <FEXCore/Utils/Event.h>
-#include <FEXHeaderUtils/Syscalls.h>
-#include <stdint.h>
-
-
-#include <atomic>
-#include <condition_variable>
-#include <functional>
-#include <istream>
-#include <map>
-#include <memory>
-#include <mutex>
-#include <shared_mutex>
-#include <stddef.h>
-#include <string>
-#include <unordered_map>
-#include <queue>
-#include <vector>
-
-namespace FEXCore {
-class CodeLoader;
-class ThunkHandler;
-class GdbServer;
-
-namespace CodeSerialize {
-  class CodeObjectSerializeService;
-}
-
-namespace CPU {
-  class Arm64JITCore;
-  class X86JITCore;
-  class InterpreterCore;
-  class Dispatcher;
-}
-namespace HLE {
-struct SyscallArguments;
-class SyscallHandler;
-class SourcecodeResolver;
-struct SourcecodeMap;
-}
-}
-
-namespace FEXCore::IR {
-  class RegisterAllocationData;
-  class IRListView;
-namespace Validation {
-  class IRValidation;
-}
-}
-
-namespace FEXCore::Context {
-  enum CoreRunningMode {
-    MODE_RUN        = 0,
-    MODE_SINGLESTEP = 1,
-  };
-
-  struct Context {
-    friend class FEXCore::HLE::SyscallHandler;
-  #ifdef JIT_ARM64
-    friend class FEXCore::CPU::Arm64JITCore;
-  #endif
-  #ifdef JIT_X86_64
-    friend class FEXCore::CPU::X86JITCore;
-  #endif
-
-    friend class FEXCore::CPU::InterpreterCore;
-    friend class FEXCore::IR::Validation::IRValidation;
-
-    struct {
-      CoreRunningMode RunningMode {CoreRunningMode::MODE_RUN};
-      uint64_t VirtualMemSize{1ULL << 36};
-
-      // this is for internal use
-      bool ValidateIRarser { false };
-
-      FEX_CONFIG_OPT(Multiblock, MULTIBLOCK);
-      FEX_CONFIG_OPT(SingleStepConfig, SINGLESTEP);
-      FEX_CONFIG_OPT(GdbServer, GDBSERVER);
-      FEX_CONFIG_OPT(Is64BitMode, IS64BIT_MODE);
-      FEX_CONFIG_OPT(TSOEnabled, TSOENABLED);
-      FEX_CONFIG_OPT(TSOAutoMigration, TSOAUTOMIGRATION);
-      FEX_CONFIG_OPT(ABILocalFlags, ABILOCALFLAGS);
-      FEX_CONFIG_OPT(ABINoPF, ABINOPF);
-      FEX_CONFIG_OPT(AOTIRCapture, AOTIRCAPTURE);
-      FEX_CONFIG_OPT(AOTIRGenerate, AOTIRGENERATE);
-      FEX_CONFIG_OPT(AOTIRLoad, AOTIRLOAD);
-      FEX_CONFIG_OPT(SMCChecks, SMCCHECKS);
-      FEX_CONFIG_OPT(Core, CORE);
-      FEX_CONFIG_OPT(MaxInstPerBlock, MAXINST);
-      FEX_CONFIG_OPT(RootFSPath, ROOTFS);
-      FEX_CONFIG_OPT(ThunkHostLibsPath, THUNKHOSTLIBS);
-      FEX_CONFIG_OPT(ThunkConfigFile, THUNKCONFIG);
-      FEX_CONFIG_OPT(DumpIR, DUMPIR);
-      FEX_CONFIG_OPT(StaticRegisterAllocation, SRA);
-      FEX_CONFIG_OPT(GlobalJITNaming, GLOBALJITNAMING);
-      FEX_CONFIG_OPT(LibraryJITNaming, LIBRARYJITNAMING);
-      FEX_CONFIG_OPT(BlockJITNaming, BLOCKJITNAMING);
-      FEX_CONFIG_OPT(GDBSymbols, GDBSYMBOLS);
-      FEX_CONFIG_OPT(ParanoidTSO, PARANOIDTSO);
-      FEX_CONFIG_OPT(CacheObjectCodeCompilation, CACHEOBJECTCODECOMPILATION);
-      FEX_CONFIG_OPT(x87ReducedPrecision, X87REDUCEDPRECISION);
-      FEX_CONFIG_OPT(x86dec_SynchronizeRIPOnAllBlocks, X86DEC_SYNCHRONIZERIPONALLBLOCKS);
-      FEX_CONFIG_OPT(EnableAVX, ENABLEAVX);
-    } Config;
-
-    FEXCore::HostFeatures HostFeatures;
-
-    std::mutex ThreadCreationMutex;
-    FEXCore::Core::InternalThreadState* ParentThread;
-    std::vector<FEXCore::Core::InternalThreadState*> Threads;
-    std::atomic_bool CoreShuttingDown{false};
-    bool NeedToCheckXID{true};
-
-    std::mutex IdleWaitMutex;
-    std::condition_variable IdleWaitCV;
-    std::atomic<uint32_t> IdleWaitRefCount{};
-
-    Event PauseWait;
-    bool Running{};
-
-    std::shared_mutex CodeInvalidationMutex;
-
-    FEXCore::CPUIDEmu CPUID;
-    FEXCore::HLE::SyscallHandler *SyscallHandler{};
-    FEXCore::HLE::SourcecodeResolver *SourcecodeResolver{};
-    std::unique_ptr<FEXCore::ThunkHandler> ThunkHandler;
-    std::unique_ptr<FEXCore::CPU::Dispatcher> Dispatcher;
-
-    CustomCPUFactoryType CustomCPUFactory;
-    FEXCore::Context::ExitHandler CustomExitHandler;
-
-#ifdef BLOCKSTATS
-    std::unique_ptr<FEXCore::BlockSamplingData> BlockData;
-#endif
-
-    SignalDelegator *SignalDelegation{};
-    X86GeneratedCode X86CodeGen;
-
-    Context();
-    ~Context();
-
-    FEXCore::Core::InternalThreadState* InitCore(uint64_t InitialRIP, uint64_t StackPointer);
-    FEXCore::Context::ExitReason RunUntilExit();
-    int GetProgramStatus() const;
-    bool IsPaused() const { return !Running; }
-    void Pause();
-    void Run();
-    void WaitForThreadsToRun();
-    void Step();
-    void Stop(bool IgnoreCurrentThread);
-    void WaitForIdle();
-    void StopThread(FEXCore::Core::InternalThreadState *Thread);
-    void SignalThread(FEXCore::Core::InternalThreadState *Thread, FEXCore::Core::SignalEvent Event);
-
-    bool GetGdbServerStatus() const { return DebugServer != nullptr; }
-    void StartGdbServer();
-    void StopGdbServer();
-    void HandleCallback(FEXCore::Core::InternalThreadState *Thread, uint64_t RIP);
-    void RegisterHostSignalHandler(int Signal, HostSignalDelegatorFunction Func, bool Required);
-    void RegisterFrontendHostSignalHandler(int Signal, HostSignalDelegatorFunction Func, bool Required);
-
-    static void ThreadRemoveCodeEntry(FEXCore::Core::InternalThreadState *Thread, uint64_t GuestRIP);
-    static void ThreadAddBlockLink(FEXCore::Core::InternalThreadState *Thread, uint64_t GuestDestination, uintptr_t HostLink, const std::function<void()> &delinker);
-
-    template<auto Fn>
-    static uint64_t ThreadExitFunctionLink(FEXCore::Core::CpuStateFrame *Frame, uint64_t *record) {
-      FHU::ScopedSignalMaskWithSharedLock lk(Frame->Thread->CTX->CodeInvalidationMutex);
-
-      return Fn(Frame, record);
-    }
-
-    // Wrapper which takes CpuStateFrame instead of InternalThreadState and unique_locks CodeInvalidationMutex
-    // Must be called from owning thread
-    static void ThreadRemoveCodeEntryFromJit(FEXCore::Core::CpuStateFrame *Frame, uint64_t GuestRIP) {
-      auto Thread = Frame->Thread;
-      
-      LogMan::Throw::AFmt(Thread->ThreadManager.GetTID() == FHU::Syscalls::gettid(), "Must be called from owning thread {}, not {}", Thread->ThreadManager.GetTID(), FHU::Syscalls::gettid());
-
-      FHU::ScopedSignalMaskWithUniqueLock lk(Thread->CTX->CodeInvalidationMutex);
-
-      ThreadRemoveCodeEntry(Thread, GuestRIP);
-    }
-
-    // returns false if a handler was already registered
-    CustomIRResult AddCustomIREntrypoint(uintptr_t Entrypoint, std::function<void(uintptr_t Entrypoint, FEXCore::IR::IREmitter *)> Handler, void *Creator, void *Data);
-
-    void RemoveCustomIREntrypoint(uintptr_t Entrypoint);
-
-    // Debugger interface
-    void CompileRIP(FEXCore::Core::InternalThreadState *Thread, uint64_t RIP);
-    uint64_t GetThreadCount() const;
-    FEXCore::Core::RuntimeStats *GetRuntimeStatsForThread(uint64_t Thread);
-    bool GetDebugDataForRIP(uint64_t RIP, FEXCore::Core::DebugData *Data);
-    bool FindHostCodeForRIP(uint64_t RIP, uint8_t **Code);
-
-    struct GenerateIRResult {
-      FEXCore::IR::IRListView* IRList;
-      FEXCore::IR::RegisterAllocationData::UniquePtr RAData;
-      uint64_t TotalInstructions;
-      uint64_t TotalInstructionsLength;
-      uint64_t StartAddr;
-      uint64_t Length;
-    };
-    [[nodiscard]] GenerateIRResult GenerateIR(FEXCore::Core::InternalThreadState *Thread, uint64_t GuestRIP, bool ExtendedDebugInfo);
-
-    struct CompileCodeResult {
-      void* CompiledCode;
-      FEXCore::IR::IRListView* IRData;
-      FEXCore::Core::DebugData* DebugData;
-      FEXCore::IR::RegisterAllocationData::UniquePtr RAData;
-      bool GeneratedIR;
-      uint64_t StartAddr;
-      uint64_t Length;
-    };
-    [[nodiscard]] CompileCodeResult CompileCode(FEXCore::Core::InternalThreadState *Thread, uint64_t GuestRIP);
-    uintptr_t CompileBlock(FEXCore::Core::CpuStateFrame *Frame, uint64_t GuestRIP);
-
-    // same as CompileBlock, but aborts on failure
-    void CompileBlockJit(FEXCore::Core::CpuStateFrame *Frame, uint64_t GuestRIP);
-
-    // Used for thread creation from syscalls
-    /**
-     * @brief Used to create FEX thread objects in preparation for creating a true OS thread. Does set a TID or PID.
-     *
-     * @param NewThreadState The initial thread state to setup for our state
-     * @param ParentTID The PID that was the parent thread that created this
-     *
-     * @return The InternalThreadState object that tracks all of the emulated thread's state
-     *
-     * Usecases:
-     *  OS thread Creation:
-     *    - Thread = CreateThread(NewState, PPID);
-     *    - InitializeThread(Thread);
-     *  OS fork (New thread created with a clone of thread state):
-     *    - clone{2, 3}
-     *    - Thread = CreateThread(CopyOfThreadState, PPID);
-     *    - ExecutionThread(Thread); // Starts executing without creating another host thread
-     *  Thunk callback executing guest code from native host thread
-     *    - Thread = CreateThread(NewState, PPID);
-     *    - InitializeThreadTLSData(Thread);
-     *    - HandleCallback(Thread, RIP);
-     */
-    FEXCore::Core::InternalThreadState* CreateThread(FEXCore::Core::CPUState *NewThreadState, uint64_t ParentTID);
-
-    /**
-     * @brief Initializes TID, PID and TLS data for a thread
-     *
-     * @param Thread The internal FEX thread state object
-     */
-    void InitializeThreadTLSData(FEXCore::Core::InternalThreadState *Thread);
-
-    /**
-     * @brief Initializes the OS thread object and prepares to start executing on that new OS thread
-     *
-     * @param Thread The internal FEX thread state object
-     *
-     * The OS thread will wait until RunThread is executed
-     */
-    void InitializeThread(FEXCore::Core::InternalThreadState *Thread);
-
-    /**
-     * @brief Starts the OS thread object to start executing guest code
-     *
-     * @param Thread The internal FEX thread state object
-     */
-    void RunThread(FEXCore::Core::InternalThreadState *Thread);
-
-    /**
-     * @brief Destroys this FEX thread object and stops tracking it internally
-     *
-     * @param Thread The internal FEX thread state object
-     */
-    void DestroyThread(FEXCore::Core::InternalThreadState *Thread);
-    void CopyMemoryMapping(FEXCore::Core::InternalThreadState *ParentThread, FEXCore::Core::InternalThreadState *ChildThread);
-
-    void CleanupAfterFork(FEXCore::Core::InternalThreadState *ExceptForThread);
-
-    std::vector<FEXCore::Core::InternalThreadState*>* GetThreads() { return &Threads; }
-
-    uint8_t GetGPRSize() const { return Config.Is64BitMode ? 8 : 4; }
-
-    IR::AOTIRCacheEntry *LoadAOTIRCacheEntry(const std::string &filename);
-    void UnloadAOTIRCacheEntry(IR::AOTIRCacheEntry *Entry);
-
-    FEXCore::JITSymbols Symbols;
-
-    // Public for threading
-    void ExecutionThread(FEXCore::Core::InternalThreadState *Thread);
-
-    void FinalizeAOTIRCache() {
-      IRCaptureCache.FinalizeAOTIRCache();
-    }
-
-    void WriteFilesWithCode(std::function<void(const std::string& fileid, const std::string& filename)> Writer) {
-      IRCaptureCache.WriteFilesWithCode(Writer);
-    }
-
-    void SetAOTIRLoader(std::function<int(const std::string&)> CacheReader) {
-      IRCaptureCache.SetAOTIRLoader(CacheReader);
-    }
-
-    void SetAOTIRWriter(std::function<std::unique_ptr<std::ofstream>(const std::string&)> CacheWriter) {
-      IRCaptureCache.SetAOTIRWriter(CacheWriter);
-    }
-
-    void SetAOTIRRenamer(std::function<void(const std::string&)> CacheRenamer) {
-      IRCaptureCache.SetAOTIRRenamer(CacheRenamer);
-    }
-
-    void AppendThunkDefinitions(std::vector<FEXCore::IR::ThunkDefinition> const& Definitions);
-
-    FEXCore::Utils::PooledAllocatorMMap OpDispatcherAllocator;
-    FEXCore::Utils::PooledAllocatorMMap FrontendAllocator;
-
-    void MarkMemoryShared();
-
-    bool IsTSOEnabled() { return (IsMemoryShared || !Config.TSOAutoMigration) && Config.TSOEnabled; }
-
-  protected:
-    void ClearCodeCache(FEXCore::Core::InternalThreadState *Thread);
-
-  private:
-    /**
-     * @brief Does some final thread initialization
-     *
-     * @param Thread The internal FEX thread state object
-     *
-     * InitCore and CreateThread both call this to finish up thread object initialization
-     */
-    void InitializeThreadData(FEXCore::Core::InternalThreadState *Thread);
-
-    /**
-     * @brief Initializes the JIT compilers for the thread
-     *
-     * @param State The internal FEX thread state object
-     *
-     * InitializeCompiler is called inside of CreateThread, so you likely don't need this
-     */
-    void InitializeCompiler(FEXCore::Core::InternalThreadState* Thread);
-
-    void WaitForIdleWithTimeout();
-
-    void NotifyPause();
-
-    void AddBlockMapping(FEXCore::Core::InternalThreadState *Thread, uint64_t Address, void *Ptr);
-
-    // Entry Cache
-    std::mutex ExitMutex;
-    std::unique_ptr<GdbServer> DebugServer;
-
-    IR::AOTIRCaptureCache IRCaptureCache;
-    std::unique_ptr<FEXCore::CodeSerialize::CodeObjectSerializeService> CodeObjectCacheService;
-
-    bool StartPaused = false;
-    bool IsMemoryShared = false;
-    FEX_CONFIG_OPT(AppFilename, APP_FILENAME);
-
-    std::shared_mutex CustomIRMutex;
-    std::unordered_map<uint64_t, std::tuple<std::function<void(uintptr_t Entrypoint, FEXCore::IR::IREmitter *)>, void *, void *>> CustomIRHandlers;
-    FEXCore::CPU::CPUBackendFeatures BackendFeatures;
-    FEXCore::CPU::DispatcherConfig DispatcherConfig;
-  };
-
-  uint64_t HandleSyscall(FEXCore::HLE::SyscallHandler *Handler, FEXCore::Core::CpuStateFrame *Frame, FEXCore::HLE::SyscallArguments *Args);
-}
@@ -1,384 +0,0 @@
-#include "Interface/Core/ArchHelpers/Arm64Emitter.h"
-#include "Interface/Core/Dispatcher/Dispatcher.h"
-#include "Interface/Context/Context.h"
-#include "Interface/HLE/Thunks/Thunks.h"
-
-#include <FEXCore/Core/CoreState.h>
-#include <FEXCore/Utils/LogManager.h>
-#include <FEXCore/Utils/MathUtils.h>
-
-#include <aarch64/cpu-aarch64.h>
-#include <aarch64/instructions-aarch64.h>
-#include <cpu-features.h>
-#include <utils-vixl.h>
-
-#include <array>
-#include <tuple>
-#include <utility>
-
-namespace FEXCore::CPU {
-
-// We want vixl to not allocate a default buffer. Jit and dispatcher will manually create one.
-Arm64Emitter::Arm64Emitter(FEXCore::Context::Context *ctx, size_t size)
-  : vixl::aarch64::Assembler(size ? (byte*)FEXCore::Allocator::mmap(nullptr, size, PROT_READ | PROT_WRITE | PROT_EXEC, MAP_PRIVATE | MAP_ANONYMOUS, -1, 0) : reinterpret_cast<byte*>(~0ULL),
-                             size,
-                             vixl::aarch64::PositionDependentCode)
-  , EmitterCTX {ctx} {
-  CPU.SetUp();
-
-#ifdef VIXL_SIMULATOR
-  auto Features = vixl::CPUFeatures::All();
-#else
-  auto Features = vixl::CPUFeatures::InferFromOS();
-  if (ctx->HostFeatures.SupportsAtomics) {
-    // Hypervisor can hide this on the c630?
-    Features.Combine(vixl::CPUFeatures::Feature::kLORegions);
-  }
-#endif
-
-  SetCPUFeatures(Features);
-}
-
-Arm64Emitter::~Arm64Emitter() {
-  auto CodeBuffer = GetBuffer();
-  if (CodeBuffer->GetCapacity()) {
-    FEXCore::Allocator::munmap(CodeBuffer->GetStartAddress<void*>(), CodeBuffer->GetCapacity());
-  }
-}
-
-void Arm64Emitter::LoadConstant(vixl::aarch64::Register Reg, uint64_t Constant, bool NOPPad) {
-  bool Is64Bit = Reg.IsX();
-  int Segments = Is64Bit ? 4 : 2;
-
-  if (Is64Bit && ((~Constant)>> 16) == 0) {
-    movn(Reg, (~Constant) & 0xFFFF);
-
-    if (NOPPad) {
-      nop(); nop(); nop();
-    }
-    return;
-  }
-
-  int NumMoves = 1;
-  int RequiredMoveSegments{};
-
-  // Count the number of move segments
-  // We only want to use ADRP+ADD if we have more than 1 segment
-  for (size_t i = 0; i < Segments; ++i) {
-    uint16_t Part = (Constant >> (i * 16)) & 0xFFFF;
-    if (Part != 0) {
-      ++RequiredMoveSegments;
-    }
-  }
-
-  // ADRP+ADD is specifically optimized in hardware
-  // Check if we can use this
-  auto PC = GetCursorAddress<uint64_t>();
-
-  // PC aligned to page
-  uint64_t AlignedPC = PC & ~0xFFFULL;
-
-  // Offset from aligned PC
-  int64_t AlignedOffset = static_cast<int64_t>(Constant) - static_cast<int64_t>(AlignedPC);
-
-  // If the aligned offset is within the 4GB window then we can use ADRP+ADD
-  // and the number of move segments more than 1
-  if (RequiredMoveSegments > 1 && vixl::IsInt32(AlignedOffset)) {
-    // If this is 4k page aligned then we only need ADRP
-    if ((AlignedOffset & 0xFFF) == 0) {
-      adrp(Reg, AlignedOffset >> 12);
-    }
-    else {
-      // If the constant is within 1MB of PC then we can still use ADR to load in a single instruction
-      // 21-bit signed integer here
-      int64_t SmallOffset = static_cast<int64_t>(Constant) - static_cast<int64_t>(PC);
-      if (vixl::IsInt21(SmallOffset)) {
-        adr(Reg, SmallOffset);
-      }
-      else {
-        // Need to use ADRP + ADD
-        adrp(Reg, AlignedOffset >> 12);
-        add(Reg, Reg, Constant & 0xFFF);
-        NumMoves = 2;
-      }
-    }
-  }
-  else {
-    movz(Reg, (Constant) & 0xFFFF, 0);
-    for (int i = 1; i < Segments; ++i) {
-      uint16_t Part = (Constant >> (i * 16)) & 0xFFFF;
-      if (Part) {
-        movk(Reg, Part, i * 16);
-        ++NumMoves;
-      }
-    }
-  }
-
-  if (NOPPad) {
-    for (int i = NumMoves; i < Segments; ++i) {
-      nop();
-    }
-  }
-}
-
-void Arm64Emitter::PushCalleeSavedRegisters() {
-  // We need to save pairs of registers
-  // We save r19-r30
-  MemOperand PairOffset(sp, -16, PreIndex);
-  const std::array<std::pair<vixl::aarch64::Register, vixl::aarch64::Register>, 6> CalleeSaved = {{
-    {x19, x20},
-    {x21, x22},
-    {x23, x24},
-    {x25, x26},
-    {x27, x28},
-    {x29, x30},
-  }};
-
-  for (auto &RegPair : CalleeSaved) {
-    stp(RegPair.first, RegPair.second, PairOffset);
-  }
-
-  // Additionally we need to store the lower 64bits of v8-v15
-  // Here's a fun thing, we can use two ST4 instructions to store everything
-  // We just need a single sub to sp before that
-  const std::array<
-    std::tuple<vixl::aarch64::VRegister,
-               vixl::aarch64::VRegister,
-               vixl::aarch64::VRegister,
-               vixl::aarch64::VRegister>, 2> FPRs = {{
-    {v8, v9, v10, v11},
-    {v12, v13, v14, v15},
-  }};
-
-  uint32_t VectorSaveSize = sizeof(uint64_t) * 8;
-  sub(sp, sp, VectorSaveSize);
-  // SP supporting move
-  // We just saved x19 so it is safe
-  add(x19, sp, 0);
-
-  MemOperand QuadOffset(x19, 32, PostIndex);
-  for (auto &RegQuad : FPRs) {
-    st4(std::get<0>(RegQuad).D(),
-        std::get<1>(RegQuad).D(),
-        std::get<2>(RegQuad).D(),
-        std::get<3>(RegQuad).D(),
-        0,
-        QuadOffset);
-  }
-}
-
-void Arm64Emitter::PopCalleeSavedRegisters() {
-  const std::array<
-    std::tuple<vixl::aarch64::VRegister,
-               vixl::aarch64::VRegister,
-               vixl::aarch64::VRegister,
-               vixl::aarch64::VRegister>, 2> FPRs = {{
-    {v12, v13, v14, v15},
-    {v8, v9, v10, v11},
-  }};
-
-  MemOperand QuadOffset(sp, 32, PostIndex);
-  for (auto &RegQuad : FPRs) {
-    ld4(std::get<0>(RegQuad).D(),
-        std::get<1>(RegQuad).D(),
-        std::get<2>(RegQuad).D(),
-        std::get<3>(RegQuad).D(),
-        0,
-        QuadOffset);
-  }
-
-  MemOperand PairOffset(sp, 16, PostIndex);
-  const std::array<std::pair<vixl::aarch64::Register, vixl::aarch64::Register>, 6> CalleeSaved = {{
-    {x29, x30},
-    {x27, x28},
-    {x25, x26},
-    {x23, x24},
-    {x21, x22},
-    {x19, x20},
-  }};
-
-  for (auto &RegPair : CalleeSaved) {
-    ldp(RegPair.first, RegPair.second, PairOffset);
-  }
-}
-
-
-void Arm64Emitter::SpillStaticRegs(bool FPRs, uint32_t GPRSpillMask, uint32_t FPRSpillMask) {
-  if (StaticRegisterAllocation()) {
-    for (size_t i = 0; i < SRA64.size(); i+=2) {
-      auto Reg1 = SRA64[i];
-      auto Reg2 = SRA64[i+1];
-      if (((1U << Reg1.GetCode()) & GPRSpillMask) &&
-          ((1U << Reg2.GetCode()) & GPRSpillMask)) {
-        stp(Reg1, Reg2, MemOperand(STATE, offsetof(FEXCore::Core::CpuStateFrame, State.gregs[i])));
-      }
-      else if (((1U << Reg1.GetCode()) & GPRSpillMask)) {
-        str(Reg1, MemOperand(STATE, offsetof(FEXCore::Core::CpuStateFrame, State.gregs[i])));
-      }
-      else if (((1U << Reg2.GetCode()) & GPRSpillMask)) {
-        str(Reg2, MemOperand(STATE, offsetof(FEXCore::Core::CpuStateFrame, State.gregs[i+1])));
-      }
-    }
-
-    if (FPRs) {
-      if (EmitterCTX->HostFeatures.SupportsAVX) {
-        for (size_t i = 0; i < SRAFPR.size(); i++) {
-          const auto Reg = SRAFPR[i];
-
-          if (((1U << Reg.GetCode()) & FPRSpillMask) != 0) {
-            mov(TMP4, offsetof(Core::CpuStateFrame, State.xmm.avx.data[i][0]));
-            st1b(Reg.Z().VnB(), PRED_TMP_32B, SVEMemOperand(STATE, TMP4));
-          }
-        }
-      } else {
-        for (size_t i = 0; i < SRAFPR.size(); i += 2) {
-          const auto Reg1 = SRAFPR[i];
-          const auto Reg2 = SRAFPR[i + 1];
-
-          if (((1U << Reg1.GetCode()) & FPRSpillMask) &&
-              ((1U << Reg2.GetCode()) & FPRSpillMask)) {
-            stp(Reg1.Q(), Reg2.Q(), MemOperand(STATE, offsetof(FEXCore::Core::CpuStateFrame, State.xmm.sse.data[i][0])));
-          }
-          else if (((1U << Reg1.GetCode()) & FPRSpillMask)) {
-            str(Reg1.Q(), MemOperand(STATE, offsetof(FEXCore::Core::CpuStateFrame, State.xmm.sse.data[i][0])));
-          }
-          else if (((1U << Reg2.GetCode()) & FPRSpillMask)) {
-            str(Reg2.Q(), MemOperand(STATE, offsetof(FEXCore::Core::CpuStateFrame, State.xmm.sse.data[i+1][0])));
-          }
-        }
-      }
-    }
-  }
-}
-
-void Arm64Emitter::FillStaticRegs(bool FPRs, uint32_t GPRFillMask, uint32_t FPRFillMask) {
-  if (StaticRegisterAllocation()) {
-    for (size_t i = 0; i < SRA64.size(); i+=2) {
-      auto Reg1 = SRA64[i];
-      auto Reg2 = SRA64[i+1];
-      if (((1U << Reg1.GetCode()) & GPRFillMask) &&
-          ((1U << Reg2.GetCode()) & GPRFillMask)) {
-        ldp(Reg1, Reg2, MemOperand(STATE, offsetof(FEXCore::Core::CpuStateFrame, State.gregs[i])));
-      }
-      else if (((1U << Reg1.GetCode()) & GPRFillMask)) {
-        ldr(Reg1, MemOperand(STATE, offsetof(FEXCore::Core::CpuStateFrame, State.gregs[i])));
-      }
-      else if (((1U << Reg2.GetCode()) & GPRFillMask)) {
-        ldr(Reg2, MemOperand(STATE, offsetof(FEXCore::Core::CpuStateFrame, State.gregs[i+1])));
-      }
-    }
-
-    if (FPRs) {
-      if (EmitterCTX->HostFeatures.SupportsAVX) {
-        // Set up predicate registers.
-        // We don't bother spilling these in SpillStaticRegs,
-        // since all that matters is we restore them on a fill.
-        // It's not a concern if they get trounced by something else.
-        ptrue(PRED_TMP_16B.VnB(), SVE_VL16);
-        ptrue(PRED_TMP_32B.VnB(), SVE_VL32);
-
-        for (size_t i = 0; i < SRAFPR.size(); i++) {
-          const auto Reg = SRAFPR[i];
-
-          if (((1U << Reg.GetCode()) & FPRFillMask) != 0) {
-            mov(TMP4, offsetof(Core::CpuStateFrame, State.xmm.avx.data[i][0]));
-            ld1b(Reg.Z().VnB(), PRED_TMP_32B.Zeroing(), SVEMemOperand(STATE, TMP4));
-          }
-        }
-      } else {
-        for (size_t i = 0; i < SRAFPR.size(); i += 2) {
-          const auto Reg1 = SRAFPR[i];
-          const auto Reg2 = SRAFPR[i + 1];
-
-          if (((1U << Reg1.GetCode()) & FPRFillMask) &&
-              ((1U << Reg2.GetCode()) & FPRFillMask)) {
-            ldp(Reg1.Q(), Reg2.Q(), MemOperand(STATE, offsetof(FEXCore::Core::CpuStateFrame, State.xmm.sse.data[i][0])));
-          }
-          else if (((1U << Reg1.GetCode()) & FPRFillMask)) {
-            ldr(Reg1.Q(), MemOperand(STATE, offsetof(FEXCore::Core::CpuStateFrame, State.xmm.sse.data[i][0])));
-          }
-          else if (((1U << Reg2.GetCode()) & FPRFillMask)) {
-            ldr(Reg2.Q(), MemOperand(STATE, offsetof(FEXCore::Core::CpuStateFrame, State.xmm.sse.data[i+1][0])));
-          }
-        }
-      }
-    }
-  }
-}
-
-void Arm64Emitter::PushDynamicRegsAndLR() {
-  const auto CanUseSVE = EmitterCTX->HostFeatures.SupportsAVX;
-  const auto GPRSize = (RA64.size() + 1) * Core::CPUState::GPR_REG_SIZE;
-  const auto FPRRegSize = CanUseSVE ? Core::CPUState::XMM_AVX_REG_SIZE
-                                    : Core::CPUState::XMM_SSE_REG_SIZE;
-  const auto FPRSize = RAFPR.size() * FPRRegSize;
-  const uint64_t SPOffset = AlignUp(GPRSize + FPRSize, 16);
-
-  sub(sp, sp, SPOffset);
-  int i = 0;
-
-  if (CanUseSVE) {
-    for (const auto& RA : RAFPR) {
-      mov(TMP4, i * 8);
-      st1b(RA.Z().VnB(), PRED_TMP_32B, SVEMemOperand(sp, TMP4));
-      i += 4;
-    }
-  } else {
-    for (const auto& RA : RAFPR) {
-      str(RA.Q(), MemOperand(sp, i * 8));
-      i += 2;
-    }
-  }
-
-#if 0 // All GPRs should be caller saved
-  for (const auto& RA : RA64) {
-    str(RA, MemOperand(sp, i * 8));
-    i++;
-  }
-#endif
-
-  str(lr, MemOperand(sp, i * 8));
-}
-
-void Arm64Emitter::PopDynamicRegsAndLR() {
-  const auto CanUseSVE = EmitterCTX->HostFeatures.SupportsAVX;
-  const auto GPRSize = (RA64.size() + 1) * Core::CPUState::GPR_REG_SIZE;
-  const auto FPRRegSize = CanUseSVE ? Core::CPUState::XMM_AVX_REG_SIZE
-                                    : Core::CPUState::XMM_SSE_REG_SIZE;
-  const auto FPRSize = RAFPR.size() * FPRRegSize;
-  const uint64_t SPOffset = AlignUp(GPRSize + FPRSize, 16);
-  int i = 0;
-
-  if (CanUseSVE) {
-    for (const auto& RA : RAFPR) {
-      mov(TMP4, i * 8);
-      ld1b(RA.Z().VnB(), PRED_TMP_32B.Zeroing(), SVEMemOperand(sp, TMP4));
-      i += 4;
-    }
-  } else {
-    for (const auto& RA : RAFPR) {
-      ldr(RA.Q(), MemOperand(sp, i * 8));
-      i += 2;
-    }
-  }
-
-#if 0 // All GPRs should be caller saved
-  for (const auto& RA : RA64) {
-    ldr(RA, MemOperand(sp, i * 8));
-    i++;
-  }
-#endif
-
-  ldr(lr, MemOperand(sp, i * 8));
-
-  add(sp, sp, SPOffset);
-}
-
-void Arm64Emitter::Align16B() {
-  uint64_t CurrentOffset = GetCursorAddress<uint64_t>();
-  for (uint64_t i = (16 - (CurrentOffset & 0xF)); i != 0; i -= 4) {
-    nop();
-  }
-}
-
-}
@@ -1,185 +0,0 @@
-#pragma once
-
-#include "Interface/Core/Dispatcher/Dispatcher.h"
-#include "Interface/Core/ObjectCache/Relocations.h"
-
-#include <aarch64/assembler-aarch64.h>
-#include <aarch64/constants-aarch64.h>
-#include <aarch64/cpu-aarch64.h>
-#include <aarch64/operands-aarch64.h>
-#include <platform-vixl.h>
-#ifdef VIXL_SIMULATOR
-#include <aarch64/simulator-aarch64.h>
-#include <aarch64/simulator-constants-aarch64.h>
-#endif
-
-#include <FEXCore/Config/Config.h>
-
-#include <array>
-#include <cstddef>
-#include <cstdint>
-#include <utility>
-
-namespace FEXCore::CPU {
-using namespace vixl;
-using namespace vixl::aarch64;
-
-// All but x29 are caller saved
-const std::array<aarch64::Register, 16> SRA64 = {
-  x4, x5, x6, x7, x8, x9, x10, x11,
-  x12, x18, x17, x16, x15, x14, x13, x29
-};
-
-// All are callee saved
-const std::array<aarch64::Register, 9> RA64 = {
-  x20, x21, x22, x23, x24, x25, x26, x27,
-  x19
-};
-
-const std::array<std::pair<aarch64::Register, aarch64::Register>, 4>  RA64Pair = {{
-  {x20, x21},
-  {x22, x23},
-  {x24, x25},
-  {x26, x27},
-}};
-
-const std::array<std::pair<aarch64::Register, aarch64::Register>, 4> RA32Pair = {{
-  {w20, w21},
-  {w22, w23},
-  {w24, w25},
-  {w26, w27},
-}};
-
-// All are caller saved
-const std::array<aarch64::VRegister, 16> SRAFPR = {
-  v16, v17, v18, v19, v20, v21, v22, v23,
-  v24, v25, v26, v27, v28, v29, v30, v31
-};
-
-//  v8..v15 = (lower 64bits) Callee saved
-const std::array<aarch64::VRegister, 12> RAFPR = {
-/*v0,  v1,  v2,  v3,*/v4,  v5,  v6,  v7,  // v0 ~ v3 are used as temps
-  v8,  v9,  v10, v11, v12, v13, v14, v15
-};
-
-// Contains the address to the currently available CPU state
-#define STATE x28
-
-// GPR temporaries. Only x3 can be used across spill boundaries
-// so if these ever need to change, be very careful about that.
-#define TMP1 x0
-#define TMP2 x1
-#define TMP3 x2
-#define TMP4 x3
-
-// Vector temporaries
-#define VTMP1 v1
-#define VTMP2 v2
-#define VTMP3 v3
-
-// Predicate register temporaries (used when AVX support is enabled)
-// PRED_TMP_16B indicates a predicate register that indicates the first 16 bytes set to 1.
-// PRED_TMP_32B indicates a predicate register that indicates the first 32 bytes set to 1.
-#define PRED_TMP_16B p6
-#define PRED_TMP_32B p7
-
-// This class contains common emitter utility functions that can
-// be used by both Arm64 JIT and ARM64 Dispatcher
-class Arm64Emitter : public vixl::aarch64::Assembler {
-protected:
-  Arm64Emitter(FEXCore::Context::Context *ctx, size_t size);
-  ~Arm64Emitter();
-
-  FEXCore::Context::Context *EmitterCTX;
-  vixl::aarch64::CPU CPU;
-  void LoadConstant(vixl::aarch64::Register Reg, uint64_t Constant, bool NOPPad = false);
-
-  // NOTE: These functions WILL clobber the register TMP4 if AVX support is enabled
-  //       and FPRs are being spilled or filled. If only GPRs are spilled/filled, then
-  //       TMP4 is left alone.
-  void SpillStaticRegs(bool FPRs = true, uint32_t GPRSpillMask = ~0U, uint32_t FPRSpillMask = ~0U);
-  void FillStaticRegs(bool FPRs = true, uint32_t GPRFillMask = ~0U, uint32_t FPRFillMask = ~0U);
-
-  static constexpr uint32_t CALLER_GPR_MASK = 0b0011'1111'1111'1111'1111;
-
-  // This isn't technically true because the lower 64-bits of v8..v15 are callee saved
-  // We can't guarantee only the lower 64bits are used so flush everything
-  static constexpr uint32_t CALLER_FPR_MASK = ~0U;
-
-  void PushDynamicRegsAndLR();
-  void PopDynamicRegsAndLR();
-
-  void PushCalleeSavedRegisters();
-  void PopCalleeSavedRegisters();
-
-  void Align16B();
-#ifdef VIXL_SIMULATOR
-  // Generates a vixl simulator runtime call.
-  //
-  // This matches behaviour of vixl's macro assembler, but we need to reimplement it since we aren't using the macro assembler.
-  // This isn't too complex with how vixl emits this.
-  //
-  // Emit:
-  // 1) hlt(kRuntimeCallOpcode)
-  // 2) Simulator wrapper handler
-  // 3) Function to call
-  // 4) Style of the function call (Call versus tail-call)
-  template<typename R, typename... P>
-  void GenerateRuntimeCall(R (*Function)(P...)) {
-    uintptr_t SimulatorWrapperAddress = reinterpret_cast<uintptr_t>(
-      &(Simulator::RuntimeCallStructHelper<R, P...>::Wrapper));
-
-    uintptr_t FunctionAddress = reinterpret_cast<uintptr_t>(Function);
-
-    hlt(kRuntimeCallOpcode);
-
-    // Simulator wrapper address pointer.
-    dc(SimulatorWrapperAddress);
-
-    // Runtime function address to call
-    dc(FunctionAddress);
-
-    // Call type
-    dc32(kCallRuntime);
-  }
-
-  template<typename R, typename... P>
-  void GenerateIndirectRuntimeCall(vixl::aarch64::Register Reg) {
-    uintptr_t SimulatorWrapperAddress = reinterpret_cast<uintptr_t>(
-      &(Simulator::RuntimeCallStructHelper<R, P...>::Wrapper));
-
-    hlt(kIndirectRuntimeCallOpcode);
-
-    // Simulator wrapper address pointer.
-    dc(SimulatorWrapperAddress);
-
-    // Register that contains the function to call
-    dc(Reg.GetCode());
-
-    // Call type
-    dc32(kCallRuntime);
-  }
-
-  template<>
-  void GenerateIndirectRuntimeCall<float, __uint128_t>(vixl::aarch64::Register Reg) {
-    uintptr_t SimulatorWrapperAddress = reinterpret_cast<uintptr_t>(
-      &(Simulator::RuntimeCallStructHelper<float, __uint128_t>::Wrapper));
-
-    hlt(kIndirectRuntimeCallOpcode);
-
-    // Simulator wrapper address pointer.
-    dc(SimulatorWrapperAddress);
-
-    // Register that contains the function to call
-    dc(Reg.GetCode());
-
-    // Call type
-    dc32(kCallRuntime);
-  }
-
-#endif
-
-  FEX_CONFIG_OPT(StaticRegisterAllocation, SRA);
-};
-
-}
@@ -1,87 +0,0 @@
-#include "Interface/Context/Context.h"
-#include "Interface/Core/Dispatcher/Dispatcher.h"
-#include <FEXCore/Core/CPUBackend.h>
-
-namespace FEXCore {
-namespace CPU {
-
-CPUBackend::CPUBackend(FEXCore::Core::InternalThreadState *ThreadState, size_t InitialCodeSize, size_t MaxCodeSize)
-    : ThreadState(ThreadState), InitialCodeSize(InitialCodeSize), MaxCodeSize(MaxCodeSize) {}
-
-CPUBackend::~CPUBackend() {
-  for (auto CodeBuffer : CodeBuffers) {
-    FreeCodeBuffer(CodeBuffer);
-  }
-  CodeBuffers.clear();
-}
-
-auto CPUBackend::GetEmptyCodeBuffer() -> CodeBuffer * {
-  if (ThreadState->CurrentFrame->SignalHandlerRefCounter == 0) {
-    if (CodeBuffers.empty()) {
-      auto NewCodeBuffer = AllocateNewCodeBuffer(InitialCodeSize);
-      EmplaceNewCodeBuffer(NewCodeBuffer);
-    } else {
-      if (CodeBuffers.size() > 1) {
-        // If we have more than one code buffer we are tracking then walk them and delete
-        // This is a cleanup step
-        for (size_t i = 1; i < CodeBuffers.size(); i++) {
-          FreeCodeBuffer(CodeBuffers[i]);
-        }
-        CodeBuffers.resize(1);
-      }
-      // Set the current code buffer to the initial
-      CurrentCodeBuffer = &CodeBuffers[0];
-
-      if (CurrentCodeBuffer->Size != MaxCodeSize) {
-        FreeCodeBuffer(*CurrentCodeBuffer);
-
-        // Resize the code buffer and reallocate our code size
-        CurrentCodeBuffer->Size *= 1.5;
-        CurrentCodeBuffer->Size = std::min(CurrentCodeBuffer->Size, MaxCodeSize);
-
-        *CurrentCodeBuffer = AllocateNewCodeBuffer(CurrentCodeBuffer->Size);
-      }
-    }
-  } else {
-    // We have signal handlers that have generated code
-    // This means that we can not safely clear the code at this point in time
-    // Allocate some new code buffers that we can switch over to instead
-    auto NewCodeBuffer = AllocateNewCodeBuffer(InitialCodeSize);
-    EmplaceNewCodeBuffer(NewCodeBuffer);
-  }
-
-  return CurrentCodeBuffer;
-}
-
-auto CPUBackend::AllocateNewCodeBuffer(size_t Size) -> CodeBuffer {
-  CodeBuffer Buffer;
-  Buffer.Size = Size;
-  Buffer.Ptr = static_cast<uint8_t *>(
-      FEXCore::Allocator::mmap(nullptr, Buffer.Size, PROT_READ | PROT_WRITE | PROT_EXEC, MAP_PRIVATE | MAP_ANONYMOUS, -1, 0));
-  LOGMAN_THROW_AA_FMT(!!Buffer.Ptr, "Couldn't allocate code buffer");
-
-  if (ThreadState->CTX->Config.GlobalJITNaming()) {
-    ThreadState->CTX->Symbols.RegisterJITSpace(Buffer.Ptr, Buffer.Size);
-  }
-  return Buffer;
-}
-
-void CPUBackend::FreeCodeBuffer(CodeBuffer Buffer) {
-  FEXCore::Allocator::munmap(Buffer.Ptr, Buffer.Size);
-}
-
-bool CPUBackend::IsAddressInCodeBuffer(uintptr_t Address) const {
-  for (auto &Buffer: CodeBuffers) {
-    auto start = (uintptr_t)Buffer.Ptr;
-    auto end = start + Buffer.Size;
-
-    if (Address >= start && Address < end) {
-      return true;
-    }
-  }
-
-  return false;
-}
-
-}
-}
@@ -1,106 +0,0 @@
-#pragma once
-
-#include <cstdint>
-#include <unordered_map>
-#include <utility>
-#include <vector>
-
-#include <FEXCore/Core/CPUID.h>
-#include <FEXCore/Config/Config.h>
-
-namespace FEXCore {
-namespace Context {
-  struct Context;
-}
-
-class CPUIDEmu final {
-private:
-  constexpr static uint32_t CPUID_VENDOR_INTEL1 = 0x756E6547; // "Genu"
-  constexpr static uint32_t CPUID_VENDOR_INTEL2 = 0x49656E69; // "ineI"
-  constexpr static uint32_t CPUID_VENDOR_INTEL3 = 0x6C65746E; // "ntel"
-
-  constexpr static uint32_t CPUID_VENDOR_AMD1 = 0x68747541; // "Auth"
-  constexpr static uint32_t CPUID_VENDOR_AMD2 = 0x69746E65; // "enti"
-  constexpr static uint32_t CPUID_VENDOR_AMD3 = 0x444D4163; // "cAMD"
-
-public:
-  // X86 cacheline size effectively has to be hardcoded to 64
-  // if we report anything differently then applications are likely to break
-  constexpr static uint64_t CACHELINE_SIZE = 64;
-
-  void Init(FEXCore::Context::Context *ctx);
-
-  FEXCore::CPUID::FunctionResults RunFunction(uint32_t Function, uint32_t Leaf) {
-    const auto Handler = FunctionHandlers.find(Function);
-
-    if (Handler == FunctionHandlers.end()) {
-      return Function_Reserved(Leaf);
-    }
-
-    return (this->*Handler->second)(Leaf);
-  }
-
-  FEXCore::CPUID::FunctionResults RunFunctionName(uint32_t Function, uint32_t Leaf, uint32_t CPU) {
-    if (Function == 0x8000'0002U)
-      return Function_8000_0002h(Leaf, CPU % PerCPUData.size());
-    else if (Function == 0x8000'0003U)
-      return Function_8000_0003h(Leaf, CPU % PerCPUData.size());
-    else
-      return Function_8000_0004h(Leaf, CPU % PerCPUData.size());
-  }
-
-private:
-  FEXCore::Context::Context *CTX;
-  bool Hybrid{};
-  FEX_CONFIG_OPT(Cores, THREADS);
-
-  using FunctionHandler = FEXCore::CPUID::FunctionResults (CPUIDEmu::*)(uint32_t Leaf);
-  void RegisterFunction(uint32_t Function, FunctionHandler Handler) {
-    FunctionHandlers.insert_or_assign(Function, Handler);
-  }
-
-  std::unordered_map<uint32_t, FunctionHandler> FunctionHandlers;
-  struct CPUData {
-    const char *ProductName{};
-#ifdef _M_ARM_64
-    uint32_t MIDR{};
-#endif
-    bool IsBig{};
-  };
-  std::vector<CPUData> PerCPUData{};
-
-  // Functions
-  FEXCore::CPUID::FunctionResults Function_0h(uint32_t Leaf);
-  FEXCore::CPUID::FunctionResults Function_01h(uint32_t Leaf);
-  FEXCore::CPUID::FunctionResults Function_02h(uint32_t Leaf);
-  FEXCore::CPUID::FunctionResults Function_04h(uint32_t Leaf);
-  FEXCore::CPUID::FunctionResults Function_06h(uint32_t Leaf);
-  FEXCore::CPUID::FunctionResults Function_07h(uint32_t Leaf);
-  FEXCore::CPUID::FunctionResults Function_0Dh(uint32_t Leaf);
-  FEXCore::CPUID::FunctionResults Function_15h(uint32_t Leaf);
-  FEXCore::CPUID::FunctionResults Function_1Ah(uint32_t Leaf);
-  FEXCore::CPUID::FunctionResults Function_4000_0000h(uint32_t Leaf);
-  FEXCore::CPUID::FunctionResults Function_4000_0001h(uint32_t Leaf);
-  FEXCore::CPUID::FunctionResults Function_8000_0000h(uint32_t Leaf);
-  FEXCore::CPUID::FunctionResults Function_8000_0001h(uint32_t Leaf);
-  FEXCore::CPUID::FunctionResults Function_8000_0002h(uint32_t Leaf);
-  FEXCore::CPUID::FunctionResults Function_8000_0003h(uint32_t Leaf);
-  FEXCore::CPUID::FunctionResults Function_8000_0004h(uint32_t Leaf);
-
-  FEXCore::CPUID::FunctionResults Function_8000_0002h(uint32_t Leaf, uint32_t CPU);
-  FEXCore::CPUID::FunctionResults Function_8000_0003h(uint32_t Leaf, uint32_t CPU);
-  FEXCore::CPUID::FunctionResults Function_8000_0004h(uint32_t Leaf, uint32_t CPU);
-
-  FEXCore::CPUID::FunctionResults Function_8000_0005h(uint32_t Leaf);
-  FEXCore::CPUID::FunctionResults Function_8000_0006h(uint32_t Leaf);
-  FEXCore::CPUID::FunctionResults Function_8000_0007h(uint32_t Leaf);
-  FEXCore::CPUID::FunctionResults Function_8000_0008h(uint32_t Leaf);
-  FEXCore::CPUID::FunctionResults Function_8000_0009h(uint32_t Leaf);
-  FEXCore::CPUID::FunctionResults Function_8000_0019h(uint32_t Leaf);
-  FEXCore::CPUID::FunctionResults Function_8000_001Dh(uint32_t Leaf);
-  FEXCore::CPUID::FunctionResults Function_Reserved(uint32_t Leaf);
-
-  void SetupHostHybridFlag();
-
-};
-}
@@ -1,23 +0,0 @@
-#pragma once
-
-namespace FEXCore {
-  class CodeLoader;
-}
-
-namespace FEXCore::Context {
-  struct Context;
-}
-
-namespace FEXCore::CPU {
-
-  /**
-   * @brief Create the CPU core backend for the context passed in
-   *
-   * @param CTX
-   *
-   * @return true if core was able to be create
-   */
-  bool CreateCPUCore(FEXCore::Context::Context *CTX);
-
-  bool LoadCode(FEXCore::Context::Context *CTX, FEXCore::CodeLoader *Loader);
-}
@@ -1,674 +0,0 @@
-#include "Interface/Core/LookupCache.h"
-
-#include "Interface/Core/ArchHelpers/MContext.h"
-#include "Interface/Core/Dispatcher/Arm64Dispatcher.h"
-#include "Interface/Core/Interpreter/InterpreterClass.h"
-
-#include "Interface/Context/Context.h"
-#include "Interface/Core/X86HelperGen.h"
-
-#include <FEXCore/Core/CPUBackend.h>
-#include <FEXCore/Core/CoreState.h>
-#include <FEXCore/Core/X86Enums.h>
-#include <FEXCore/Debug/InternalThreadState.h>
-#include <FEXHeaderUtils/Syscalls.h>
-
-#include <array>
-#include <bit>
-#include <cmath>
-#include <cstddef>
-#include <cstdint>
-#include <memory>
-
-#include <aarch64/assembler-aarch64.h>
-#include <aarch64/constants-aarch64.h>
-#include <aarch64/cpu-aarch64.h>
-#include <aarch64/operands-aarch64.h>
-#include <code-buffer-vixl.h>
-#include <platform-vixl.h>
-
-#include <sys/syscall.h>
-#include <unistd.h>
-
-#define STATE_PTR(STATE_TYPE, FIELD) \
-  MemOperand(STATE, offsetof(FEXCore::Core::STATE_TYPE, FIELD))
-
-namespace FEXCore::CPU {
-
-using namespace vixl;
-using namespace vixl::aarch64;
-
-constexpr size_t MAX_DISPATCHER_CODE_SIZE = 8192;
-
-Arm64Dispatcher::Arm64Dispatcher(FEXCore::Context::Context *ctx, const DispatcherConfig &config)
-  : FEXCore::CPU::Dispatcher(ctx, config), Arm64Emitter(ctx, MAX_DISPATCHER_CODE_SIZE)
-#ifdef VIXL_SIMULATOR
-  , Simulator {&Decoder}
-#endif
-{
-
-#ifdef VIXL_SIMULATOR
-  // Hardcode a 256-bit vector width if we are running in the simulator.
-  Simulator.SetVectorLengthInBits(256);
-#endif
-
-  SetAllowAssembler(true);
-
-  DispatchPtr = GetCursorAddress<AsmDispatch>();
-
-  // while (true) {
-  //    Ptr = FindBlock(RIP)
-  //    if (!Ptr)
-  //      Ptr = CTX->CompileBlock(RIP);
-  //
-  //    Ptr();
-  // }
-
-  Literal l_CTX {reinterpret_cast<uintptr_t>(CTX)};
-  Literal l_Sleep {reinterpret_cast<uint64_t>(SleepThread)};
-  Literal l_CompileBlock {GetCompileBlockPtr()};
-
-  // Push all the register we need to save
-  PushCalleeSavedRegisters();
-
-  // Push our memory base to the correct register
-  // Move our thread pointer to the correct register
-  // This is passed in to parameter 0 (x0)
-  mov(STATE, x0);
-
-  // Save this stack pointer so we can cleanly shutdown the emulation with a long jump
-  // regardless of where we were in the stack
-  add(x0, sp, 0);
-  str(x0, STATE_PTR(CpuStateFrame, ReturningStackLocation));
-
-  AbsoluteLoopTopAddressFillSRA = GetCursorAddress<uint64_t>();
-
-  if (config.StaticRegisterAllocation) {
-    FillStaticRegs();
-  }
-
-  // We want to ensure that we are 16 byte aligned at the top of this loop
-  Align16B();
-  aarch64::Label FullLookup{};
-  aarch64::Label CallBlock{};
-  aarch64::Label LoopTop{};
-  aarch64::Label ExitSpillSRA{};
-  aarch64::Label ThreadPauseHandler{};
-
-  bind(&LoopTop);
-  AbsoluteLoopTopAddress = GetLabelAddress<uint64_t>(&LoopTop);
-
-  // Load in our RIP
-  // Don't modify x2 since it contains our RIP once the block doesn't exist
-  ldr(x2, STATE_PTR(CpuStateFrame, State.rip));
-  auto RipReg = x2;
-
-  // L1 Cache
-  ldr(x0, STATE_PTR(CpuStateFrame, Pointers.Common.L1Pointer));
-
-  and_(x3, RipReg, LookupCache::L1_ENTRIES_MASK);
-  add(x0, x0, Operand(x3, Shift::LSL, 4));
-  ldp(x3, x0, MemOperand(x0));
-  cmp(x0, RipReg);
-  b(&FullLookup, Condition::ne);
-
-  br(x3);
-
-  // L1C check failed, do a full lookup
-  bind(&FullLookup);
-
-  // This is the block cache lookup routine
-  // It matches what is going on it LookupCache.h::FindBlock
-  ldr(x0, STATE_PTR(CpuStateFrame, Pointers.Common.L2Pointer));
-
-  // Mask the address by the virtual address size so we can check for aliases
-  uint64_t VirtualMemorySize = CTX->Config.VirtualMemSize;
-  if (std::popcount(VirtualMemorySize) == 1) {
-    and_(x3, RipReg, VirtualMemorySize - 1);
-  }
-  else {
-    LoadConstant(x3, VirtualMemorySize);
-    and_(x3, RipReg, x3);
-  }
-
-  aarch64::Label NoBlock;
-  {
-    // Offset the address and add to our page pointer
-    lsr(x1, x3, 12);
-
-    // Load the pointer from the offset
-    ldr(x0, MemOperand(x0, x1, Shift::LSL, 3));
-
-    // If page pointer is zero then we have no block
-    cbz(x0, &NoBlock);
-
-    // Steal the page offset
-    and_(x1, x3, 0x0FFF);
-
-    // Shift the offset by the size of the block cache entry
-    add(x0, x0, Operand(x1, Shift::LSL, (int)log2(sizeof(FEXCore::LookupCache::LookupCacheEntry))));
-
-    // Load the guest address first to ensure it maps to the address we are currently at
-    // This fixes aliasing problems
-    ldr(x1, MemOperand(x0, offsetof(FEXCore::LookupCache::LookupCacheEntry, GuestCode)));
-    cmp(x1, RipReg);
-    b(&NoBlock, Condition::ne);
-
-    // Now load the actual host block to execute if we can
-    ldr(x3, MemOperand(x0, offsetof(FEXCore::LookupCache::LookupCacheEntry, HostCode)));
-    cbz(x3, &NoBlock);
-
-    // If we've made it here then we have a real compiled block
-    {
-      // update L1 cache
-      ldr(x0, STATE_PTR(CpuStateFrame, Pointers.Common.L1Pointer));
-
-      and_(x1, RipReg, LookupCache::L1_ENTRIES_MASK);
-      add(x0, x0, Operand(x1, Shift::LSL, 4));
-      stp(x3, x2, MemOperand(x0));
-
-      // Jump to the block
-      br(x3);
-    }
-  }
-
-  {
-    bind(&ExitSpillSRA);
-    ThreadStopHandlerAddressSpillSRA = GetCursorAddress<uint64_t>();
-    if (config.StaticRegisterAllocation)
-      SpillStaticRegs();
-
-    ThreadStopHandlerAddress = GetCursorAddress<uint64_t>();
-
-    PopCalleeSavedRegisters();
-
-    // Return from the function
-    // LR is set to the correct return location now
-    ret();
-  }
-
-#ifdef VIXL_SIMULATOR
-  // VIXL simulator can't run syscalls.
-  constexpr bool SignalSafeCompile = false;
-#else
-  constexpr bool SignalSafeCompile = true;
-#endif
-  {
-    ExitFunctionLinkerAddress = GetCursorAddress<uint64_t>();
-    if (config.StaticRegisterAllocation)
-      SpillStaticRegs();
-
-    if (SignalSafeCompile) {
-      // When compiling code, mask all signals to reduce the chance of reentrant allocations
-      // Args:
-      // X0: SETMASK
-      // X1: Pointer to mask value (uint64_t)
-      // X2: Pointer to old mask value (uint64_t)
-      // X3: Size of mask, sizeof(uint64_t)
-      // X8: Syscall
-
-      LoadConstant(x0, ~0ULL);
-      stp(x0, x0, MemOperand(sp, -16, PreIndex));
-      LoadConstant(x0, SIG_SETMASK);
-      add(x1, sp, 0);
-      add(x2, sp, 0);
-      LoadConstant(x3, 8);
-      LoadConstant(x8, SYS_rt_sigprocmask);
-      svc(0);
-    }
-
-    mov(x0, STATE);
-    mov(x1, lr);
-
-    ldr(x2, STATE_PTR(CpuStateFrame, Pointers.Common.ExitFunctionLink));
-#ifdef VIXL_SIMULATOR
-    GenerateIndirectRuntimeCall<uintptr_t, void *, void *>(x2);
-#else
-    blr(x2);
-#endif
-
-    if (SignalSafeCompile) {
-      // Now restore the signal mask
-      // Living in the same location
-
-      mov(x4, x0);
-      LoadConstant(x0, SIG_SETMASK);
-      add(x1, sp, 0);
-      LoadConstant(x2, 0);
-      LoadConstant(x3, 8);
-      LoadConstant(x8, SYS_rt_sigprocmask);
-      svc(0);
-
-      // Bring stack back
-      add(sp, sp, 16);
-
-      mov(x0, x4);
-    }
-
-    if (config.StaticRegisterAllocation)
-      FillStaticRegs();
-    br(x0);
-  }
-
-  // Need to create the block
-  {
-    bind(&NoBlock);
-
-    if (config.StaticRegisterAllocation)
-      SpillStaticRegs();
-
-    if (SignalSafeCompile) {
-      // When compiling code, mask all signals to reduce the chance of reentrant allocations
-      // Args:
-      // X0: SETMASK
-      // X1: Pointer to mask value (uint64_t)
-      // X2: Pointer to old mask value (uint64_t)
-      // X3: Size of mask, sizeof(uint64_t)
-      // X8: Syscall
-
-      LoadConstant(x0, ~0ULL);
-      stp(x0, x2, MemOperand(sp, -16, PreIndex));
-      LoadConstant(x0, SIG_SETMASK);
-      add(x1, sp, 0);
-      add(x2, sp, 0);
-      LoadConstant(x3, 8);
-      LoadConstant(x8, SYS_rt_sigprocmask);
-      svc(0);
-
-      // Reload x2 to bring back RIP
-      ldr(x2, MemOperand(sp, 8, Offset));
-    }
-
-    ldr(x0, &l_CTX);
-    mov(x1, STATE);
-    ldr(x3, &l_CompileBlock);
-
-    // X2 contains our guest RIP
-#ifdef VIXL_SIMULATOR
-    GenerateIndirectRuntimeCall<void, void *, uint64_t, void *>(x3);
-#else
-    blr(x3); // { CTX, Frame, RIP}
-#endif
-
-    if (SignalSafeCompile) {
-      // Now restore the signal mask
-      // Living in the same location
-      LoadConstant(x0, SIG_SETMASK);
-      add(x1, sp, 0);
-      LoadConstant(x2, 0);
-      LoadConstant(x3, 8);
-      LoadConstant(x8, SYS_rt_sigprocmask);
-      svc(0);
-
-      // Bring stack back
-      add(sp, sp, 16);
-    }
-
-    if (config.StaticRegisterAllocation)
-      FillStaticRegs();
-
-    b(&LoopTop);
-  }
-
-  {
-    SignalHandlerReturnAddress = GetCursorAddress<uint64_t>();
-
-    // Now to get back to our old location we need to do a fault dance
-    // We can't use SIGTRAP here since gdb catches it and never gives it to the application!
-    hlt(0);
-  }
-
-  {
-    // Guest SIGILL handler
-    // Needs to be distinct from the SignalHandlerReturnAddress
-    GuestSignal_SIGILL  = GetCursorAddress<uint64_t>();
-
-    if (config.StaticRegisterAllocation)
-      SpillStaticRegs();
-
-    hlt(0);
-  }
-
-  {
-    // Guest SIGTRAP handler
-    // Needs to be distinct from the SignalHandlerReturnAddress
-    GuestSignal_SIGTRAP  = GetCursorAddress<uint64_t>();
-
-    if (config.StaticRegisterAllocation)
-      SpillStaticRegs();
-
-    brk(0);
-  }
-
-  {
-    // Guest Overflow handler
-    // Needs to be distinct from the SignalHandlerReturnAddress
-    GuestSignal_SIGSEGV = GetCursorAddress<uint64_t>();
-
-    if (config.StaticRegisterAllocation)
-      SpillStaticRegs();
-
-    // hlt/udf = SIGILL
-    // brk = SIGTRAP
-    // ??? = SIGSEGV
-    // Force a SIGSEGV by loading zero
-    LoadConstant(x1, 0);
-    ldr(x1, MemOperand(x1));
-  }
-
-  {
-    ThreadPauseHandlerAddressSpillSRA = GetCursorAddress<uint64_t>();
-    if (config.StaticRegisterAllocation)
-      SpillStaticRegs();
-
-    bind(&ThreadPauseHandler);
-    ThreadPauseHandlerAddress = GetCursorAddress<uint64_t>();
-    // We are pausing, this means the frontend should be waiting for this thread to idle
-    // We will have faulted and jumped to this location at this point
-
-    // Call our sleep handler
-    ldr(x0, &l_CTX);
-    mov(x1, STATE);
-    ldr(x2, &l_Sleep);
-#ifdef VIXL_SIMULATOR
-    GenerateIndirectRuntimeCall<void, void *, void *>(x2);
-#else
-    blr(x2);
-#endif
-
-    PauseReturnInstruction = GetCursorAddress<uint64_t>();
-    // Fault to start running again
-    hlt(0);
-  }
-
-  {
-    // The expectation here is that a thunked function needs to call back in to the JIT in a reentrant safe way
-    // To do this safely we need to do some state tracking and register saving
-    //
-    // eg:
-    // JIT Call->
-    //  Thunk->
-    //    Thunk callback->
-    //
-    // The thunk callback needs to execute JIT code and when it returns, it needs to safely return to the thunk rather than JIT space
-    // This is handled by pushing a return address trampoline to the stack so when the guest address returns it hits our custom thunk return
-    //  - This will safely return us to the thunk
-    //
-    // On return to the thunk, the thunk can get whatever its return value is from the thread context depending on ABI handling on its end
-    // When the thunk itself returns, it'll do its regular return logic there
-    // void ReentrantCallback(FEXCore::Core::InternalThreadState *Thread, uint64_t RIP);
-    CallbackPtr = GetCursorAddress<JITCallback>();
-
-    // We expect the thunk to have previously pushed the registers it was using
-    PushCalleeSavedRegisters();
-
-    // First thing we need to move the thread state pointer back in to our register
-    mov(STATE, x0);
-
-    // Make sure to adjust the refcounter so we don't clear the cache now
-    ldr(w2, STATE_PTR(CpuStateFrame, SignalHandlerRefCounter));
-    add(w2, w2, 1);
-    str(w2, STATE_PTR(CpuStateFrame, SignalHandlerRefCounter));
-
-    // Now push the callback return trampoline to the guest stack
-    // Guest will be misaligned because calling a thunk won't correct the guest's stack once we call the callback from the host
-    LoadConstant(x0, CTX->X86CodeGen.CallbackReturn);
-
-    ldr(x2, STATE_PTR(CpuStateFrame, State.gregs[X86State::REG_RSP]));
-    sub(x2, x2, 16);
-    str(x2, STATE_PTR(CpuStateFrame, State.gregs[X86State::REG_RSP]));
-
-    // Store the trampoline to the guest stack
-    // Guest stack is now correctly misaligned after a regular call instruction
-    str(x0, MemOperand(x2));
-
-    // Store RIP to the context state
-    str(x1, STATE_PTR(CpuStateFrame, State.rip));
-
-    // load static regs
-    if (config.StaticRegisterAllocation)
-      FillStaticRegs();
-
-    // Now go back to the regular dispatcher loop
-    b(&LoopTop);
-  }
-
-  {
-    LUDIVHandlerAddress = GetCursorAddress<uint64_t>();
-
-    PushDynamicRegsAndLR();
-    SpillStaticRegs();
-
-    ldr(x3, STATE_PTR(CpuStateFrame, Pointers.AArch64.LUDIV));
-#ifdef VIXL_SIMULATOR
-    GenerateIndirectRuntimeCall<uint64_t, uint64_t, uint64_t, uint64_t>(x3);
-#else
-    blr(x3);
-#endif
-    FillStaticRegs();
-
-    // Result is now in x0
-    // Fix the stack and any values that were stepped on
-    PopDynamicRegsAndLR();
-
-    // Go back to our code block
-    ret();
-  }
-
-  {
-    LDIVHandlerAddress = GetCursorAddress<uint64_t>();
-
-    PushDynamicRegsAndLR();
-    SpillStaticRegs();
-
-    ldr(x3, STATE_PTR(CpuStateFrame, Pointers.AArch64.LDIV));
-#ifdef VIXL_SIMULATOR
-    GenerateIndirectRuntimeCall<uint64_t, uint64_t, uint64_t, uint64_t>(x3);
-#else
-    blr(x3);
-#endif
-    FillStaticRegs();
-
-    // Result is now in x0
-    // Fix the stack and any values that were stepped on
-    PopDynamicRegsAndLR();
-
-    // Go back to our code block
-    ret();
-  }
-
-  {
-    LUREMHandlerAddress = GetCursorAddress<uint64_t>();
-
-    PushDynamicRegsAndLR();
-    SpillStaticRegs();
-
-    ldr(x3, STATE_PTR(CpuStateFrame, Pointers.AArch64.LUREM));
-#ifdef VIXL_SIMULATOR
-    GenerateIndirectRuntimeCall<uint64_t, uint64_t, uint64_t, uint64_t>(x3);
-#else
-    blr(x3);
-#endif
-    FillStaticRegs();
-
-    // Result is now in x0
-    // Fix the stack and any values that were stepped on
-    PopDynamicRegsAndLR();
-
-    // Go back to our code block
-    ret();
-  }
-
-  {
-    LREMHandlerAddress = GetCursorAddress<uint64_t>();
-
-    PushDynamicRegsAndLR();
-    SpillStaticRegs();
-
-    ldr(x3, STATE_PTR(CpuStateFrame, Pointers.AArch64.LREM));
-#ifdef VIXL_SIMULATOR
-    GenerateIndirectRuntimeCall<uint64_t, uint64_t, uint64_t, uint64_t>(x3);
-#else
-    blr(x3);
-#endif
-    FillStaticRegs();
-
-    // Result is now in x0
-    // Fix the stack and any values that were stepped on
-    PopDynamicRegsAndLR();
-
-    // Go back to our code block
-    ret();
-  }
-
-  place(&l_CTX);
-  place(&l_Sleep);
-  place(&l_CompileBlock);
-
-
-  FinalizeCode();
-  Start = reinterpret_cast<uint64_t>(DispatchPtr);
-  End = GetCursorAddress<uint64_t>();
-  vixl::aarch64::CPU::EnsureIAndDCacheCoherency(reinterpret_cast<void*>(DispatchPtr), End - reinterpret_cast<uint64_t>(DispatchPtr));
-  GetBuffer()->SetExecutable();
-
-  if (CTX->Config.BlockJITNaming()) {
-    std::string Name = "Dispatch_" + std::to_string(FHU::Syscalls::gettid());
-    CTX->Symbols.Register(reinterpret_cast<void*>(DispatchPtr), End - reinterpret_cast<uint64_t>(DispatchPtr), Name);
-  }
-  if (CTX->Config.GlobalJITNaming()) {
-    CTX->Symbols.RegisterJITSpace(reinterpret_cast<void*>(DispatchPtr), End - reinterpret_cast<uint64_t>(DispatchPtr));
-  }
-}
-
-#ifdef VIXL_SIMULATOR
-void Arm64Dispatcher::ExecuteDispatch(FEXCore::Core::CpuStateFrame *Frame) {
-  Simulator.WriteXRegister(0, reinterpret_cast<int64_t>(Frame));
-  Simulator.RunFrom(reinterpret_cast<Instruction const*>(DispatchPtr));
-}
-
-void Arm64Dispatcher::ExecuteJITCallback(FEXCore::Core::CpuStateFrame *Frame, uint64_t RIP) {
-  Simulator.WriteXRegister(0, reinterpret_cast<int64_t>(Frame));
-  Simulator.WriteXRegister(1, RIP);
-  Simulator.RunFrom(reinterpret_cast<Instruction const*>(CallbackPtr));
-}
-
-#endif
-
-// Used by GenerateGDBPauseCheck, GenerateInterpreterTrampoline, destination buffer is set before use
-static thread_local vixl::aarch64::Assembler emit((uint8_t*)&emit, 1);
-
-size_t Arm64Dispatcher::GenerateGDBPauseCheck(uint8_t *CodeBuffer, uint64_t GuestRIP) {
-
-  *emit.GetBuffer() = vixl::CodeBuffer(CodeBuffer, MaxGDBPauseCheckSize);
-
-  vixl::CodeBufferCheckScope scope(&emit, MaxGDBPauseCheckSize, vixl::CodeBufferCheckScope::kDontReserveBufferSpace, vixl::CodeBufferCheckScope::kNoAssert);
-
-  aarch64::Label RunBlock;
-
-  // If we have a gdb server running then run in a less efficient mode that checks if we need to exit
-  // This happens when single stepping
-
-  static_assert(sizeof(FEXCore::Context::Context::Config.RunningMode) == 4, "This is expected to be size of 4");
-  emit.ldr(x0, STATE_PTR(CpuStateFrame, Thread)); // Get thread
-  emit.ldr(x0, MemOperand(x0, offsetof(FEXCore::Core::InternalThreadState, CTX))); // Get Context
-  emit.ldr(w0, MemOperand(x0, offsetof(FEXCore::Context::Context, Config.RunningMode)));
-
-  // If the value == 0 then we don't need to stop
-  emit.cbz(w0, &RunBlock);
-  {
-    Literal l_GuestRIP {GuestRIP};
-    // Make sure RIP is syncronized to the context
-    emit.ldr(x0, &l_GuestRIP);
-    emit.str(x0, STATE_PTR(CpuStateFrame, State.rip));
-
-    // Stop the thread
-    emit.ldr(x0, STATE_PTR(CpuStateFrame, Pointers.Common.ThreadPauseHandlerSpillSRA));
-    emit.br(x0);
-    emit.place(&l_GuestRIP);
-  }
-  emit.bind(&RunBlock);
-  emit.FinalizeCode();
-
-  auto UsedBytes = emit.GetBuffer()->GetCursorOffset();
-  vixl::aarch64::CPU::EnsureIAndDCacheCoherency(CodeBuffer, UsedBytes);
-  return UsedBytes;
-}
-
-size_t Arm64Dispatcher::GenerateInterpreterTrampoline(uint8_t *CodeBuffer) {
-  LOGMAN_THROW_AA_FMT(!config.StaticRegisterAllocation, "GenerateInterpreterTrampoline dispatcher does not support SRA");
-
-  *emit.GetBuffer() = vixl::CodeBuffer(CodeBuffer, MaxInterpreterTrampolineSize);
-
-  vixl::CodeBufferCheckScope scope(&emit, MaxInterpreterTrampolineSize, vixl::CodeBufferCheckScope::kDontReserveBufferSpace, vixl::CodeBufferCheckScope::kNoAssert);
-
-  aarch64::Label InlineIRData;
-
-  emit.mov(x0, STATE);
-  emit.adr(x1, &InlineIRData);
-
-  emit.ldr(x3, STATE_PTR(CpuStateFrame, Pointers.Interpreter.FragmentExecuter));
-  emit.blr(x3);
-
-  emit.ldr(x0, STATE_PTR(CpuStateFrame, Pointers.Common.DispatcherLoopTop));
-  emit.br(x0);
-
-  emit.bind(&InlineIRData);
-
-  emit.FinalizeCode();
-
-  auto UsedBytes = emit.GetBuffer()->GetCursorOffset();
-  vixl::aarch64::CPU::EnsureIAndDCacheCoherency(CodeBuffer, UsedBytes);
-  return UsedBytes;
-}
-
-void Arm64Dispatcher::SpillSRA(FEXCore::Core::InternalThreadState *Thread, void *ucontext, uint32_t IgnoreMask) {
-  for (size_t i = 0; i < SRA64.size(); i++) {
-    if (IgnoreMask & (1U << SRA64[i].GetCode())) {
-      // Skip this one, it's already spilled
-      continue;
-    }
-    Thread->CurrentFrame->State.gregs[i] = ArchHelpers::Context::GetArmReg(ucontext, SRA64[i].GetCode());
-  }
-
-  if (EmitterCTX->HostFeatures.SupportsAVX) {
-    for (size_t i = 0; i < SRAFPR.size(); i++) {
-      auto FPR = ArchHelpers::Context::GetArmFPR(ucontext, SRAFPR[i].GetCode());
-      memcpy(&Thread->CurrentFrame->State.xmm.avx.data[i][0], &FPR, sizeof(__uint128_t));
-    }
-  } else {
-    for (size_t i = 0; i < SRAFPR.size(); i++) {
-      auto FPR = ArchHelpers::Context::GetArmFPR(ucontext, SRAFPR[i].GetCode());
-      memcpy(&Thread->CurrentFrame->State.xmm.sse.data[i][0], &FPR, sizeof(__uint128_t));
-    }
-  }
-}
-
-void Arm64Dispatcher::InitThreadPointers(FEXCore::Core::InternalThreadState *Thread) {
-  // Setup dispatcher specific pointers that need to be accessed from JIT code
-  {
-    auto &Common = Thread->CurrentFrame->Pointers.Common;
-
-    Common.DispatcherLoopTop = AbsoluteLoopTopAddress;
-    Common.DispatcherLoopTopFillSRA = AbsoluteLoopTopAddressFillSRA;
-    Common.ExitFunctionLinker = ExitFunctionLinkerAddress;
-    Common.ThreadStopHandlerSpillSRA = ThreadStopHandlerAddressSpillSRA;
-    Common.ThreadPauseHandlerSpillSRA = ThreadPauseHandlerAddressSpillSRA;
-    Common.GuestSignal_SIGILL = GuestSignal_SIGILL;
-    Common.GuestSignal_SIGTRAP = GuestSignal_SIGTRAP;
-    Common.GuestSignal_SIGSEGV = GuestSignal_SIGSEGV;
-    Common.SignalReturnHandler = SignalHandlerReturnAddress;
-
-    auto &AArch64 = Thread->CurrentFrame->Pointers.AArch64;
-    AArch64.LUDIVHandler = LUDIVHandlerAddress;
-    AArch64.LDIVHandler = LDIVHandlerAddress;
-    AArch64.LUREMHandler = LUREMHandlerAddress;
-    AArch64.LREMHandler = LREMHandlerAddress;
-  }
-}
-
-std::unique_ptr<Dispatcher> Dispatcher::CreateArm64(FEXCore::Context::Context *CTX, const DispatcherConfig &Config) {
-  return std::make_unique<Arm64Dispatcher>(CTX, Config);
-}
-
-}
@@ -1,842 +0,0 @@
-
-#include "Interface/Context/Context.h"
-#include "Interface/Core/ArchHelpers/MContext.h"
-#include "Interface/Core/Dispatcher/Dispatcher.h"
-#include "Interface/Core/X86HelperGen.h"
-
-#include <FEXCore/Config/Config.h>
-#include <FEXCore/Core/CoreState.h>
-#include <FEXCore/Core/SignalDelegator.h>
-#include <FEXCore/Core/UContext.h>
-#include <FEXCore/Core/X86Enums.h>
-#include <FEXCore/Debug/InternalThreadState.h>
-#include <FEXCore/Utils/Event.h>
-#include <FEXCore/Utils/LogManager.h>
-#include <FEXCore/Utils/MathUtils.h>
-
-#include <atomic>
-#include <condition_variable>
-#include <csignal>
-#include <cstring>
-#include <signal.h>
-
-namespace FEXCore::CPU {
-
-void Dispatcher::SleepThread(FEXCore::Context::Context *ctx, FEXCore::Core::CpuStateFrame *Frame) {
-  auto Thread = Frame->Thread;
-
-  --ctx->IdleWaitRefCount;
-  ctx->IdleWaitCV.notify_all();
-
-  Thread->RunningEvents.ThreadSleeping = true;
-
-  // Go to sleep
-  Thread->StartRunning.Wait();
-
-  Thread->RunningEvents.Running = true;
-  ++ctx->IdleWaitRefCount;
-  Thread->RunningEvents.ThreadSleeping = false;
-
-  ctx->IdleWaitCV.notify_all();
-}
-
-ArchHelpers::Context::ContextBackup* Dispatcher::StoreThreadState(FEXCore::Core::InternalThreadState *Thread, int Signal, void *ucontext) {
-  // We can end up getting a signal at any point in our host state
-  // Jump to a handler that saves all state so we can safely return
-  uint64_t OldSP = ArchHelpers::Context::GetSp(ucontext);
-  uintptr_t NewSP = OldSP;
-
-  size_t StackOffset = sizeof(ArchHelpers::Context::ContextBackup);
-
-  // We need to back up behind the host's red zone
-  // We do this on the guest side as well
-  // (does nothing on arm hosts)
-  NewSP -= ArchHelpers::Context::ContextBackup::RedZoneSize;
-
-  NewSP -= StackOffset;
-  NewSP = AlignDown(NewSP, 16);
-
-  auto Context = reinterpret_cast<ArchHelpers::Context::ContextBackup*>(NewSP);
-  ArchHelpers::Context::BackupContext(ucontext, Context);
-
-  // Retain the action pointer so we can see it when we return
-  Context->Signal = Signal;
-
-  // Save guest state
-  // We can't guarantee if registers are in context or host GPRs
-  // So we need to save everything
-  memcpy(&Context->GuestState, Thread->CurrentFrame, sizeof(FEXCore::Core::CPUState));
-
-  // Set the new SP
-  ArchHelpers::Context::SetSp(ucontext, NewSP);
-
-  // Signal frames are only used on the interpreter
-  // The JITS require the stack to be setup correctly on rt_sigreturn
-  if (CTX->Config.Core() == FEXCore::Config::CONFIG_INTERPRETER) {
-    SignalFrames.push(NewSP);
-  }
-
-  Context->Flags = 0;
-  Context->FPStateLocation = 0;
-  Context->UContextLocation = 0;
-  Context->SigInfoLocation = 0;
-
-  // Store fault to top status and then reset it
-  Context->FaultToTopAndGeneratedException = Thread->CurrentFrame->SynchronousFaultData.FaultToTopAndGeneratedException;
-  Thread->CurrentFrame->SynchronousFaultData.FaultToTopAndGeneratedException = false;
-
-  return Context;
-}
-
-void Dispatcher::RestoreThreadState(FEXCore::Core::InternalThreadState *Thread, void *ucontext) {
-  uint64_t OldSP{};
-  if (CTX->Config.Core() == FEXCore::Config::CONFIG_IRJIT) {
-    OldSP = ArchHelpers::Context::GetSp(ucontext);
-  }
-  else {
-    LOGMAN_THROW_A_FMT(!SignalFrames.empty(), "Trying to restore a signal frame when we don't have any");
-    OldSP = SignalFrames.top();
-    SignalFrames.pop();
-  }
-
-  const bool IsAVXEnabled = CTX->Config.EnableAVX;
-  uintptr_t NewSP = OldSP;
-  auto Context = reinterpret_cast<ArchHelpers::Context::ContextBackup*>(NewSP);
-
-  // First thing, reset the guest state
-  memcpy(Thread->CurrentFrame, &Context->GuestState, sizeof(FEXCore::Core::CPUState));
-
-  // Now restore host state
-  ArchHelpers::Context::RestoreContext(ucontext, Context);
-
-  if (Context->UContextLocation) {
-    auto Frame = Thread->CurrentFrame;
-
-    if (Context->Flags &ArchHelpers::Context::ContextFlags::CONTEXT_FLAG_INJIT) {
-      // XXX: Unsupported since it needs state reconstruction
-      // If we are in the JIT then SRA might need to be restored to values from the context
-      // We can't currently support this since it might result in tearing without real state reconstruction
-    }
-
-    if (!(Context->Flags & ArchHelpers::Context::ContextFlags::CONTEXT_FLAG_32BIT)) {
-      auto *guest_uctx = reinterpret_cast<FEXCore::x86_64::ucontext_t*>(Context->UContextLocation);
-      [[maybe_unused]] auto *guest_siginfo = reinterpret_cast<siginfo_t*>(Context->SigInfoLocation);
-
-      // If the guest modified the RIP then we need to take special precautions here
-      if (Context->OriginalRIP != guest_uctx->uc_mcontext.gregs[FEXCore::x86_64::FEX_REG_RIP] ||
-          Context->FaultToTopAndGeneratedException) {
-        // Hack! Go back to the top of the dispatcher top
-        // This is only safe inside the JIT rather than anything outside of it
-        ArchHelpers::Context::SetPc(ucontext, AbsoluteLoopTopAddressFillSRA);
-        // Set our state register to point to our guest thread data
-        ArchHelpers::Context::SetState(ucontext, reinterpret_cast<uint64_t>(Frame));
-
-        Frame->State.rip = guest_uctx->uc_mcontext.gregs[FEXCore::x86_64::FEX_REG_RIP];
-        // XXX: Full context setting
-        uint32_t eflags = guest_uctx->uc_mcontext.gregs[FEXCore::x86_64::FEX_REG_EFL];
-        for (size_t i = 0; i < Core::CPUState::NUM_EFLAG_BITS; ++i) {
-          Frame->State.flags[i] = (eflags & (1U << i)) ? 1 : 0;
-        }
-
-        Frame->State.flags[1] = 1;
-        Frame->State.flags[9] = 1;
-
-#define COPY_REG(x) \
-            Frame->State.gregs[X86State::REG_##x] = guest_uctx->uc_mcontext.gregs[FEXCore::x86_64::FEX_REG_##x];
-            COPY_REG(R8);
-            COPY_REG(R9);
-            COPY_REG(R10);
-            COPY_REG(R11);
-            COPY_REG(R12);
-            COPY_REG(R13);
-            COPY_REG(R14);
-            COPY_REG(R15);
-            COPY_REG(RDI);
-            COPY_REG(RSI);
-            COPY_REG(RBP);
-            COPY_REG(RBX);
-            COPY_REG(RDX);
-            COPY_REG(RAX);
-            COPY_REG(RCX);
-            COPY_REG(RSP);
-#undef COPY_REG
-        auto *xstate = reinterpret_cast<x86_64::xstate*>(guest_uctx->uc_mcontext.fpregs);
-        auto *fpstate = &xstate->fpstate;
-
-        // Copy float registers
-        memcpy(Frame->State.mm, fpstate->_st, sizeof(Frame->State.mm));
-
-        if (IsAVXEnabled) {
-          for (size_t i = 0; i < Core::CPUState::NUM_XMMS; i++) {
-            memcpy(&Frame->State.xmm.avx.data[i][0], &fpstate->_xmm[i], sizeof(__uint128_t));
-          }
-          for (size_t i = 0; i < Core::CPUState::NUM_XMMS; i++) {
-            memcpy(&Frame->State.xmm.avx.data[i][2], &xstate->ymmh.ymmh_space[i], sizeof(__uint128_t));
-          }
-        } else {
-          memcpy(Frame->State.xmm.sse.data, fpstate->_xmm, sizeof(Frame->State.xmm.sse.data));
-        }
-
-        // FCW store default
-        Frame->State.FCW = fpstate->fcw;
-        Frame->State.FTW = fpstate->ftw;
-
-        // Deconstruct FSW
-        Frame->State.flags[FEXCore::X86State::X87FLAG_C0_LOC] = (fpstate->fsw >> 8) & 1;
-        Frame->State.flags[FEXCore::X86State::X87FLAG_C1_LOC] = (fpstate->fsw >> 9) & 1;
-        Frame->State.flags[FEXCore::X86State::X87FLAG_C2_LOC] = (fpstate->fsw >> 10) & 1;
-        Frame->State.flags[FEXCore::X86State::X87FLAG_C3_LOC] = (fpstate->fsw >> 14) & 1;
-        Frame->State.flags[FEXCore::X86State::X87FLAG_TOP_LOC] = (fpstate->fsw >> 11) & 0b111;
-      }
-    }
-    else {
-      auto *guest_uctx = reinterpret_cast<FEXCore::x86::ucontext_t*>(Context->UContextLocation);
-      [[maybe_unused]] auto *guest_siginfo = reinterpret_cast<FEXCore::x86::siginfo_t*>(Context->SigInfoLocation);
-      // If the guest modified the RIP then we need to take special precautions here
-      if (Context->OriginalRIP != guest_uctx->uc_mcontext.gregs[FEXCore::x86::FEX_REG_EIP] ||
-          Context->FaultToTopAndGeneratedException) {
-        // Hack! Go back to the top of the dispatcher top
-        // This is only safe inside the JIT rather than anything outside of it
-        ArchHelpers::Context::SetPc(ucontext, AbsoluteLoopTopAddressFillSRA);
-        // Set our state register to point to our guest thread data
-        ArchHelpers::Context::SetState(ucontext, reinterpret_cast<uint64_t>(Frame));
-
-        // XXX: Full context setting
-        // First 32-bytes of flags is EFLAGS broken out
-        uint32_t eflags = guest_uctx->uc_mcontext.gregs[FEXCore::x86::FEX_REG_EFL];
-        for (size_t i = 0; i < Core::CPUState::NUM_EFLAG_BITS; ++i) {
-          Frame->State.flags[i] = (eflags & (1U << i)) ? 1 : 0;
-        }
-
-        Frame->State.flags[1] = 1;
-        Frame->State.flags[9] = 1;
-
-        Frame->State.rip = guest_uctx->uc_mcontext.gregs[FEXCore::x86::FEX_REG_EIP];
-        Frame->State.cs_idx = guest_uctx->uc_mcontext.gregs[FEXCore::x86::FEX_REG_CS];
-        Frame->State.ds_idx = guest_uctx->uc_mcontext.gregs[FEXCore::x86::FEX_REG_DS];
-        Frame->State.es_idx = guest_uctx->uc_mcontext.gregs[FEXCore::x86::FEX_REG_ES];
-        Frame->State.fs_idx = guest_uctx->uc_mcontext.gregs[FEXCore::x86::FEX_REG_FS];
-        Frame->State.gs_idx = guest_uctx->uc_mcontext.gregs[FEXCore::x86::FEX_REG_GS];
-        Frame->State.ss_idx = guest_uctx->uc_mcontext.gregs[FEXCore::x86::FEX_REG_SS];
-
-        Frame->State.cs_cached = Frame->State.gdt[Frame->State.cs_idx >> 3].base;
-        Frame->State.ds_cached = Frame->State.gdt[Frame->State.ds_idx >> 3].base;
-        Frame->State.es_cached = Frame->State.gdt[Frame->State.es_idx >> 3].base;
-        Frame->State.fs_cached = Frame->State.gdt[Frame->State.fs_idx >> 3].base;
-        Frame->State.gs_cached = Frame->State.gdt[Frame->State.gs_idx >> 3].base;
-        Frame->State.ss_cached = Frame->State.gdt[Frame->State.ss_idx >> 3].base;
-
-#define COPY_REG(x) \
-      Frame->State.gregs[X86State::REG_##x] = guest_uctx->uc_mcontext.gregs[FEXCore::x86::FEX_REG_##x];
-        COPY_REG(RDI);
-        COPY_REG(RSI);
-        COPY_REG(RBP);
-        COPY_REG(RBX);
-        COPY_REG(RDX);
-        COPY_REG(RAX);
-        COPY_REG(RCX);
-        COPY_REG(RSP);
-#undef COPY_REG
-        auto *xstate = reinterpret_cast<x86::xstate*>(guest_uctx->uc_mcontext.fpregs);
-        auto *fpstate = &xstate->fpstate;
-
-        // Copy float registers
-        for (size_t i = 0; i < Core::CPUState::NUM_MMS; ++i) {
-          // 32-bit st register size is only 10 bytes. Not padded to 16byte like x86-64
-          memcpy(&Frame->State.mm[i], &fpstate->_st[i], 10);
-        }
-
-        // Extended XMM state
-        if (IsAVXEnabled) {
-          for (size_t i = 0; i < Core::CPUState::NUM_XMMS; i++) {
-            memcpy(&fpstate->_xmm[i], &Frame->State.xmm.avx.data[i][0], sizeof(__uint128_t));
-          }
-          for (size_t i = 0; i < Core::CPUState::NUM_XMMS; i++) {
-            memcpy(&xstate->ymmh.ymmh_space[i], &Frame->State.xmm.avx.data[i][2], sizeof(__uint128_t));
-          }
-        } else {
-          memcpy(Frame->State.xmm.sse.data, fpstate->_xmm, sizeof(Frame->State.xmm.sse.data));
-        }
-
-        // FCW store default
-        Frame->State.FCW = fpstate->fcw;
-        Frame->State.FTW = fpstate->ftw;
-
-        // Deconstruct FSW
-        Frame->State.flags[FEXCore::X86State::X87FLAG_C0_LOC] = (fpstate->fsw >> 8) & 1;
-        Frame->State.flags[FEXCore::X86State::X87FLAG_C1_LOC] = (fpstate->fsw >> 9) & 1;
-        Frame->State.flags[FEXCore::X86State::X87FLAG_C2_LOC] = (fpstate->fsw >> 10) & 1;
-        Frame->State.flags[FEXCore::X86State::X87FLAG_C3_LOC] = (fpstate->fsw >> 14) & 1;
-        Frame->State.flags[FEXCore::X86State::X87FLAG_TOP_LOC] = (fpstate->fsw >> 11) & 0b111;
-      }
-    }
-  }
-}
-
-static uint32_t ConvertSignalToTrapNo(int Signal, siginfo_t *HostSigInfo) {
-  switch (Signal) {
-    case SIGSEGV:
-      if (HostSigInfo->si_code == SEGV_MAPERR ||
-          HostSigInfo->si_code == SEGV_ACCERR) {
-        // Protection fault
-        return X86State::X86_TRAPNO_PF;
-      }
-      break;
-  }
-
-  // Unknown mapping, fall back to old behaviour and just pass signal
-  return Signal;
-}
-
-static uint32_t ConvertSignalToError(int Signal, siginfo_t *HostSigInfo) {
-  switch (Signal) {
-    case SIGSEGV:
-      if (HostSigInfo->si_code == SEGV_MAPERR ||
-          HostSigInfo->si_code == SEGV_ACCERR) {
-        // Protection fault
-        // Always a user fault for us
-        // XXX: PF_PROT and PF_WRITE
-        return X86State::X86_PF_USER;
-      }
-      break;
-  }
-
-  // Not a page fault issue
-  return 0;
-}
-
-template <typename T>
-static void SetXStateInfo(T* xstate, bool is_avx_enabled) {
-  auto* fpstate = &xstate->fpstate;
-
-  fpstate->sw_reserved.magic1 = x86_64::fpx_sw_bytes::FP_XSTATE_MAGIC;
-  fpstate->sw_reserved.extended_size = is_avx_enabled ? sizeof(T) : 0;
-
-  fpstate->sw_reserved.xfeatures |= x86_64::fpx_sw_bytes::FEATURE_FP |
-                                    x86_64::fpx_sw_bytes::FEATURE_SSE;
-  if (is_avx_enabled) {
-    fpstate->sw_reserved.xfeatures |= x86_64::fpx_sw_bytes::FEATURE_YMM;
-  }
-
-  fpstate->sw_reserved.xstate_size = fpstate->sw_reserved.extended_size;
-
-  if (is_avx_enabled) {
-    xstate->xstate_hdr.xfeatures = 0;
-  }
-}
-
-bool Dispatcher::HandleGuestSignal(FEXCore::Core::InternalThreadState *Thread, int Signal, void *info, void *ucontext, GuestSigAction *GuestAction, stack_t *GuestStack) {
-  auto ContextBackup = StoreThreadState(Thread, Signal, ucontext);
-
-  auto Frame = Thread->CurrentFrame;
-
-  // Ref count our faults
-  // We use this to track if it is safe to clear cache
-  ++Thread->CurrentFrame->SignalHandlerRefCounter;
-
-  uint64_t OldPC = ArchHelpers::Context::GetPc(ucontext);
-  // Set the new PC
-  ArchHelpers::Context::SetPc(ucontext, AbsoluteLoopTopAddressFillSRA);
-  // Set our state register to point to our guest thread data
-  ArchHelpers::Context::SetState(ucontext, reinterpret_cast<uint64_t>(Frame));
-
-  uint64_t OldGuestSP = Frame->State.gregs[X86State::REG_RSP];
-  uint64_t NewGuestSP = OldGuestSP;
-
-  // Pulling from context here
-  const bool Is64BitMode = CTX->Config.Is64BitMode;
-  const bool IsAVXEnabled = CTX->Config.EnableAVX;
-  const uint64_t SignalReturn = CTX->X86CodeGen.SignalReturn;
-
-  // Spill the SRA regardless of signal handler type
-  // We are going to be returning to the top of the dispatcher which will fill again
-  // Otherwise we might load garbage
-  if (config.StaticRegisterAllocation) {
-    if (Thread->CPUBackend->IsAddressInCodeBuffer(OldPC)) {
-      uint32_t IgnoreMask{};
-#ifdef _M_ARM_64
-      if (Frame->InSyscallInfo != 0) {
-        // We are in a syscall, this means we are in a weird register state
-        // We need to spill SRA but only some of it, since some values have already been spilled
-        // Lower 16 bits tells us which registers are already spilled to the context
-        // So we ignore spilling those ones
-        uint16_t NumRegisters = std::popcount(Frame->InSyscallInfo & 0xFFFF);
-        if (NumRegisters >= 4) {
-          // Unhandled case
-          IgnoreMask = 0;
-        }
-        else {
-          IgnoreMask = Frame->InSyscallInfo & 0xFFFF;
-        }
-      }
-      else {
-        // We must spill everything
-        IgnoreMask = 0;
-      }
-#endif
-
-      // We are in jit, SRA must be spilled
-      SpillSRA(Thread, ucontext, IgnoreMask);
-
-      ContextBackup->Flags |= ArchHelpers::Context::ContextFlags::CONTEXT_FLAG_INJIT;
-    } else {
-      if (!IsAddressInDispatcher(OldPC)) {
-        // This is likely to cause issues but in some cases it isn't fatal
-        // This can also happen if we have put a signal on hold, then we just reenabled the signal
-        // So we are in the syscall handler
-        // Only throw a log message in this case
-        if constexpr (false) {
-          // XXX: Messages in the signal handler can cause us to crash
-          LogMan::Msg::EFmt("Signals in dispatcher have unsynchronized context");
-        }
-      }
-    }
-  }
-
-  // altstack is only used if the signal handler was setup with SA_ONSTACK
-  if (GuestAction->sa_flags & SA_ONSTACK) {
-    // Additionally the altstack is only used if the enabled (SS_DISABLE flag is not set)
-    if (!(GuestStack->ss_flags & SS_DISABLE)) {
-      // If our guest is already inside of the alternative stack
-      // Then that means we are hitting recursive signals and we need to walk back the stack correctly
-      uint64_t AltStackBase = reinterpret_cast<uint64_t>(GuestStack->ss_sp);
-      uint64_t AltStackEnd = AltStackBase + GuestStack->ss_size;
-      if (OldGuestSP >= AltStackBase &&
-          OldGuestSP <= AltStackEnd) {
-        // We are already in the alt stack, the rest of the code will handle adjusting this
-      }
-      else {
-        NewGuestSP = AltStackEnd;
-      }
-    }
-  }
-
-  if (Is64BitMode) {
-    // Back up past the redzone, which is 128bytes
-    // 32-bit doesn't have a redzone
-    NewGuestSP -= 128;
-  }
-
-  // siginfo_t
-  siginfo_t *HostSigInfo = reinterpret_cast<siginfo_t*>(info);
-
-  // Backup where we think the RIP currently is
-  ContextBackup->OriginalRIP = Frame->State.rip;
-
-  if (GuestAction->sa_flags & SA_SIGINFO) {
-    // Setup ucontext a bit
-    if (Is64BitMode) {
-      if (IsAVXEnabled) {
-        NewGuestSP -= sizeof(x86_64::xstate);
-        NewGuestSP = AlignDown(NewGuestSP, alignof(x86_64::xstate));
-      } else {
-        NewGuestSP -= sizeof(x86_64::_libc_fpstate);
-        NewGuestSP = AlignDown(NewGuestSP, alignof(x86_64::_libc_fpstate));
-      }
-      uint64_t FPStateLocation = NewGuestSP;
-
-      NewGuestSP -= sizeof(FEXCore::x86_64::ucontext_t);
-      NewGuestSP = AlignDown(NewGuestSP, alignof(FEXCore::x86_64::ucontext_t));
-      uint64_t UContextLocation = NewGuestSP;
-
-      NewGuestSP -= sizeof(siginfo_t);
-      NewGuestSP = AlignDown(NewGuestSP, alignof(siginfo_t));
-      uint64_t SigInfoLocation = NewGuestSP;
-
-      ContextBackup->FPStateLocation = FPStateLocation;
-      ContextBackup->UContextLocation = UContextLocation;
-      ContextBackup->SigInfoLocation = SigInfoLocation;
-
-      FEXCore::x86_64::ucontext_t *guest_uctx = reinterpret_cast<FEXCore::x86_64::ucontext_t*>(UContextLocation);
-      siginfo_t *guest_siginfo = reinterpret_cast<siginfo_t*>(SigInfoLocation);
-
-      // We have extended float information
-      guest_uctx->uc_flags = FEXCore::x86_64::UC_FP_XSTATE;
-
-      // Pointer to where the fpreg memory is
-      guest_uctx->uc_mcontext.fpregs = reinterpret_cast<x86_64::_libc_fpstate*>(FPStateLocation);
-      auto *xstate = reinterpret_cast<x86_64::xstate*>(FPStateLocation);
-      SetXStateInfo(xstate, IsAVXEnabled);
-
-      guest_uctx->uc_mcontext.gregs[FEXCore::x86_64::FEX_REG_RIP] = Frame->State.rip;
-      guest_uctx->uc_mcontext.gregs[FEXCore::x86_64::FEX_REG_EFL] = 0;
-      guest_uctx->uc_mcontext.gregs[FEXCore::x86_64::FEX_REG_CSGSFS] = 0;
-
-      // aarch64 and x86_64 siginfo_t matches. We can just copy this over
-      // SI_USER could also potentially have random data in it, needs to be bit perfect
-      // For guest faults we don't have a real way to reconstruct state to a real guest RIP
-      *guest_siginfo = *HostSigInfo;
-
-      if (ContextBackup->FaultToTopAndGeneratedException) {
-        guest_uctx->uc_mcontext.gregs[FEXCore::x86_64::FEX_REG_TRAPNO] = Frame->SynchronousFaultData.TrapNo;
-        guest_uctx->uc_mcontext.gregs[FEXCore::x86_64::FEX_REG_ERR] = Frame->SynchronousFaultData.err_code;
-
-        // Overwrite si_code
-        guest_siginfo->si_code = Thread->CurrentFrame->SynchronousFaultData.si_code;
-        Signal = Frame->SynchronousFaultData.Signal;
-      }
-      else {
-        guest_uctx->uc_mcontext.gregs[FEXCore::x86_64::FEX_REG_TRAPNO] = ConvertSignalToTrapNo(Signal, HostSigInfo);
-        guest_uctx->uc_mcontext.gregs[FEXCore::x86_64::FEX_REG_ERR] = ConvertSignalToError(Signal, HostSigInfo);
-      }
-      guest_uctx->uc_mcontext.gregs[FEXCore::x86_64::FEX_REG_OLDMASK] = 0;
-      guest_uctx->uc_mcontext.gregs[FEXCore::x86_64::FEX_REG_CR2] = 0;
-
-#define COPY_REG(x) \
-      guest_uctx->uc_mcontext.gregs[FEXCore::x86_64::FEX_REG_##x] = Frame->State.gregs[X86State::REG_##x];
-      COPY_REG(R8);
-      COPY_REG(R9);
-      COPY_REG(R10);
-      COPY_REG(R11);
-      COPY_REG(R12);
-      COPY_REG(R13);
-      COPY_REG(R14);
-      COPY_REG(R15);
-      COPY_REG(RDI);
-      COPY_REG(RSI);
-      COPY_REG(RBP);
-      COPY_REG(RBX);
-      COPY_REG(RDX);
-      COPY_REG(RAX);
-      COPY_REG(RCX);
-      COPY_REG(RSP);
-#undef COPY_REG
-
-      auto* fpstate = &xstate->fpstate;
-
-      // Copy float registers
-      memcpy(fpstate->_st, Frame->State.mm, sizeof(Frame->State.mm));
-
-      if (IsAVXEnabled) {
-        for (size_t i = 0; i < Core::CPUState::NUM_XMMS; i++) {
-          memcpy(&fpstate->_xmm[i], &Frame->State.xmm.avx.data[i][0], sizeof(__uint128_t));
-        }
-        for (size_t i = 0; i < Core::CPUState::NUM_XMMS; i++) {
-          memcpy(&xstate->ymmh.ymmh_space[i], &Frame->State.xmm.avx.data[i][2], sizeof(__uint128_t));
-        }
-      } else {
-        memcpy(fpstate->_xmm, Frame->State.xmm.sse.data, sizeof(Frame->State.xmm.sse.data));
-      }
-
-      // FCW store default
-      fpstate->fcw = Frame->State.FCW;
-      fpstate->ftw = Frame->State.FTW;
-
-      // Reconstruct FSW
-      fpstate->fsw =
-        (Frame->State.flags[FEXCore::X86State::X87FLAG_TOP_LOC] << 11) |
-        (Frame->State.flags[FEXCore::X86State::X87FLAG_C0_LOC] << 8) |
-        (Frame->State.flags[FEXCore::X86State::X87FLAG_C1_LOC] << 9) |
-        (Frame->State.flags[FEXCore::X86State::X87FLAG_C2_LOC] << 10) |
-        (Frame->State.flags[FEXCore::X86State::X87FLAG_C3_LOC] << 14);
-
-      // Copy over signal stack information
-      guest_uctx->uc_stack.ss_flags = GuestStack->ss_flags;
-      guest_uctx->uc_stack.ss_sp = GuestStack->ss_sp;
-      guest_uctx->uc_stack.ss_size = GuestStack->ss_size;
-
-      Frame->State.gregs[X86State::REG_RSI] = SigInfoLocation;
-      Frame->State.gregs[X86State::REG_RDX] = UContextLocation;
-    }
-    else {
-      ContextBackup->Flags |= ArchHelpers::Context::ContextFlags::CONTEXT_FLAG_32BIT;
-
-      if (IsAVXEnabled) {
-        NewGuestSP -= sizeof(x86::xstate);
-        NewGuestSP = AlignDown(NewGuestSP, alignof(x86::xstate));
-      } else {
-        NewGuestSP -= sizeof(x86::_libc_fpstate);
-        NewGuestSP = AlignDown(NewGuestSP, alignof(x86::_libc_fpstate));
-      }
-      uint64_t FPStateLocation = NewGuestSP;
-
-      NewGuestSP -= sizeof(FEXCore::x86::ucontext_t);
-      NewGuestSP = AlignDown(NewGuestSP, alignof(FEXCore::x86::ucontext_t));
-      uint64_t UContextLocation = NewGuestSP;
-
-      NewGuestSP -= sizeof(FEXCore::x86::siginfo_t);
-      NewGuestSP = AlignDown(NewGuestSP, alignof(FEXCore::x86::siginfo_t));
-      uint64_t SigInfoLocation = NewGuestSP;
-
-      ContextBackup->FPStateLocation = FPStateLocation;
-      ContextBackup->UContextLocation = UContextLocation;
-      ContextBackup->SigInfoLocation = SigInfoLocation;
-
-      FEXCore::x86::ucontext_t *guest_uctx = reinterpret_cast<FEXCore::x86::ucontext_t*>(UContextLocation);
-      FEXCore::x86::siginfo_t *guest_siginfo = reinterpret_cast<FEXCore::x86::siginfo_t*>(SigInfoLocation);
-
-      // We have extended float information
-      guest_uctx->uc_flags = FEXCore::x86::UC_FP_XSTATE;
-
-      // Pointer to where the fpreg memory is
-      guest_uctx->uc_mcontext.fpregs = static_cast<uint32_t>(FPStateLocation);
-      auto *xstate = reinterpret_cast<x86::xstate*>(FPStateLocation);
-      SetXStateInfo(xstate, IsAVXEnabled);
-
-      guest_uctx->uc_mcontext.gregs[FEXCore::x86::FEX_REG_CS] = Frame->State.cs_idx;
-      guest_uctx->uc_mcontext.gregs[FEXCore::x86::FEX_REG_DS] = Frame->State.ds_idx;
-      guest_uctx->uc_mcontext.gregs[FEXCore::x86::FEX_REG_ES] = Frame->State.es_idx;
-      guest_uctx->uc_mcontext.gregs[FEXCore::x86::FEX_REG_FS] = Frame->State.fs_idx;
-      guest_uctx->uc_mcontext.gregs[FEXCore::x86::FEX_REG_GS] = Frame->State.gs_idx;
-      guest_uctx->uc_mcontext.gregs[FEXCore::x86::FEX_REG_SS] = Frame->State.ss_idx;
-
-      if (ContextBackup->FaultToTopAndGeneratedException) {
-        guest_uctx->uc_mcontext.gregs[FEXCore::x86::FEX_REG_TRAPNO] = Frame->SynchronousFaultData.TrapNo;
-        guest_siginfo->si_code = Frame->SynchronousFaultData.si_code;
-        guest_uctx->uc_mcontext.gregs[FEXCore::x86::FEX_REG_ERR] = Frame->SynchronousFaultData.err_code;
-        Signal = Frame->SynchronousFaultData.Signal;
-      }
-      else {
-        guest_uctx->uc_mcontext.gregs[FEXCore::x86::FEX_REG_TRAPNO] = ConvertSignalToTrapNo(Signal, HostSigInfo);
-        guest_siginfo->si_code = HostSigInfo->si_code;
-        guest_uctx->uc_mcontext.gregs[FEXCore::x86::FEX_REG_ERR] = ConvertSignalToError(Signal, HostSigInfo);
-      }
-      guest_uctx->uc_mcontext.gregs[FEXCore::x86::FEX_REG_EIP] = Frame->State.rip;
-      guest_uctx->uc_mcontext.gregs[FEXCore::x86::FEX_REG_EFL] = 0;
-      guest_uctx->uc_mcontext.gregs[FEXCore::x86::FEX_REG_UESP] = 0;
-
-#define COPY_REG(x) \
-      guest_uctx->uc_mcontext.gregs[FEXCore::x86::FEX_REG_##x] = Frame->State.gregs[X86State::REG_##x];
-      COPY_REG(RDI);
-      COPY_REG(RSI);
-      COPY_REG(RBP);
-      COPY_REG(RBX);
-      COPY_REG(RDX);
-      COPY_REG(RAX);
-      COPY_REG(RCX);
-      COPY_REG(RSP);
-#undef COPY_REG
-
-      auto *fpstate = &xstate->fpstate;
-
-      // Copy float registers
-      for (size_t i = 0; i < Core::CPUState::NUM_MMS; ++i) {
-        // 32-bit st register size is only 10 bytes. Not padded to 16byte like x86-64
-        memcpy(&fpstate->_st[i], &Frame->State.mm[i], 10);
-      }
-
-      // Extended XMM state
-      fpstate->status = FEXCore::x86::fpstate_magic::MAGIC_XFPSTATE;
-      if (IsAVXEnabled) {
-        for (size_t i = 0; i < std::size(Frame->State.xmm.avx.data); i++) {
-          memcpy(&fpstate->_xmm[i], &Frame->State.xmm.avx.data[i][0], sizeof(__uint128_t));
-        }
-        for (size_t i = 0; i < std::size(Frame->State.xmm.avx.data); i++) {
-          memcpy(&xstate->ymmh.ymmh_space[i], &Frame->State.xmm.avx.data[i][2], sizeof(__uint128_t));
-        }
-      } else {
-        memcpy(fpstate->_xmm, Frame->State.xmm.sse.data, sizeof(Frame->State.xmm.sse.data));
-      }
-
-      // FCW store default
-      fpstate->fcw = Frame->State.FCW;
-      fpstate->ftw = Frame->State.FTW;
-      // Reconstruct FSW
-      fpstate->fsw =
-        (Frame->State.flags[FEXCore::X86State::X87FLAG_TOP_LOC] << 11) |
-        (Frame->State.flags[FEXCore::X86State::X87FLAG_C0_LOC] << 8) |
-        (Frame->State.flags[FEXCore::X86State::X87FLAG_C1_LOC] << 9) |
-        (Frame->State.flags[FEXCore::X86State::X87FLAG_C2_LOC] << 10) |
-        (Frame->State.flags[FEXCore::X86State::X87FLAG_C3_LOC] << 14);
-
-      // Copy over signal stack information
-      guest_uctx->uc_stack.ss_flags = GuestStack->ss_flags;
-      guest_uctx->uc_stack.ss_sp = static_cast<uint32_t>(reinterpret_cast<uint64_t>(GuestStack->ss_sp));
-      guest_uctx->uc_stack.ss_size = GuestStack->ss_size;
-
-      // These three elements are in every siginfo
-      guest_siginfo->si_signo = HostSigInfo->si_signo;
-      guest_siginfo->si_errno = HostSigInfo->si_errno;
-
-      switch (Signal) {
-        case SIGSEGV:
-        case SIGBUS:
-          // Macro expansion to get the si_addr
-          // This is the address trying to be accessed, not the RIP
-          guest_siginfo->_sifields._sigfault.addr = static_cast<uint32_t>(reinterpret_cast<uintptr_t>(HostSigInfo->si_addr));
-          break;
-        case SIGFPE:
-        case SIGILL:
-          // Macro expansion to get the si_addr
-          // Can't really give a real result here. Pull from the context for now
-          guest_siginfo->_sifields._sigfault.addr = Frame->State.rip;
-          break;
-        case SIGCHLD:
-          guest_siginfo->_sifields._sigchld.pid = HostSigInfo->si_pid;
-          guest_siginfo->_sifields._sigchld.uid = HostSigInfo->si_uid;
-          guest_siginfo->_sifields._sigchld.status = HostSigInfo->si_status;
-          guest_siginfo->_sifields._sigchld.utime = HostSigInfo->si_utime;
-          guest_siginfo->_sifields._sigchld.stime = HostSigInfo->si_stime;
-          break;
-        case SIGALRM:
-        case SIGVTALRM:
-          guest_siginfo->_sifields._timer.tid = HostSigInfo->si_timerid;
-          guest_siginfo->_sifields._timer.overrun = HostSigInfo->si_overrun;
-          guest_siginfo->_sifields._timer.sigval.sival_int = HostSigInfo->si_int;
-          break;
-        default:
-          LogMan::Msg::EFmt("Unhandled siginfo_t for signal: {}\n", Signal);
-          break;
-      }
-
-      NewGuestSP -= 4;
-      *(uint32_t*)NewGuestSP = UContextLocation;
-      NewGuestSP -= 4;
-      *(uint32_t*)NewGuestSP = SigInfoLocation;
-      NewGuestSP -= 4;
-      *(uint32_t*)NewGuestSP = Signal;
-    }
-
-    Frame->State.rip = reinterpret_cast<uint64_t>(GuestAction->sigaction_handler.sigaction);
-  }
-  else {
-    if (!Is64BitMode) {
-      NewGuestSP -= 4;
-      *(uint32_t*)NewGuestSP = Signal;
-    }
-
-    Frame->State.rip = reinterpret_cast<uint64_t>(GuestAction->sigaction_handler.handler);
-  }
-
-  if (Is64BitMode) {
-    Frame->State.gregs[FEXCore::X86State::REG_RDI] = Signal;
-
-    // Set up the new SP for stack handling
-    NewGuestSP -= 8;
-    *(uint64_t*)NewGuestSP = SignalReturn;
-    Frame->State.gregs[FEXCore::X86State::REG_RSP] = NewGuestSP;
-  }
-  else {
-    NewGuestSP -= 4;
-    *(uint32_t*)NewGuestSP = SignalReturn;
-    LOGMAN_THROW_AA_FMT(SignalReturn < 0x1'0000'0000ULL, "This needs to be below 4GB");
-    Frame->State.gregs[FEXCore::X86State::REG_RSP] = NewGuestSP;
-  }
-
-  // The guest starts its signal frame with a zero initialized FPU
-  // Set that up now. Little bit costly but it's a requirement
-  // This state will be restored on rt_sigreturn
-  memset(Frame->State.xmm.avx.data, 0, sizeof(Frame->State.xmm));
-  memset(Frame->State.mm, 0, sizeof(Frame->State.mm));
-  Frame->State.FCW = 0x37F;
-  Frame->State.FTW = 0xFFFF;
-
-  return true;
-}
-
-bool Dispatcher::HandleSIGILL(FEXCore::Core::InternalThreadState *Thread, int Signal, void *info, void *ucontext) {
-
-  if (ArchHelpers::Context::GetPc(ucontext) == SignalHandlerReturnAddress) {
-    RestoreThreadState(Thread, ucontext);
-
-    // Ref count our faults
-    // We use this to track if it is safe to clear cache
-    --Thread->CurrentFrame->SignalHandlerRefCounter;
-    return true;
-  }
-
-  if (ArchHelpers::Context::GetPc(ucontext) == PauseReturnInstruction) {
-    RestoreThreadState(Thread, ucontext);
-
-    // Ref count our faults
-    // We use this to track if it is safe to clear cache
-    --Thread->CurrentFrame->SignalHandlerRefCounter;
-    return true;
-  }
-
-  return false;
-}
-
-bool Dispatcher::HandleSignalPause(FEXCore::Core::InternalThreadState *Thread, int Signal, void *info, void *ucontext) {
-  FEXCore::Core::SignalEvent SignalReason = Thread->SignalReason.load();
-  auto Frame = Thread->CurrentFrame;
-
-  if (SignalReason == FEXCore::Core::SignalEvent::Pause) {
-    // Store our thread state so we can come back to this
-    StoreThreadState(Thread, Signal, ucontext);
-
-    if (config.StaticRegisterAllocation && Thread->CPUBackend->IsAddressInCodeBuffer(ArchHelpers::Context::GetPc(ucontext))) {
-      // We are in jit, SRA must be spilled
-      ArchHelpers::Context::SetPc(ucontext, ThreadPauseHandlerAddressSpillSRA);
-    } else {
-      if (config.StaticRegisterAllocation) {
-        // We are in non-jit, SRA is already spilled
-        LOGMAN_THROW_A_FMT(!IsAddressInDispatcher(ArchHelpers::Context::GetPc(ucontext)),
-                           "Signals in dispatcher have unsynchronized context");
-      }
-      ArchHelpers::Context::SetPc(ucontext, ThreadPauseHandlerAddress);
-    }
-
-    // Set our state register to point to our guest thread data
-    ArchHelpers::Context::SetState(ucontext, reinterpret_cast<uint64_t>(Frame));
-
-    // Ref count our faults
-    // We use this to track if it is safe to clear cache
-    ++Thread->CurrentFrame->SignalHandlerRefCounter;
-
-    Thread->SignalReason.store(FEXCore::Core::SignalEvent::Nothing);
-    return true;
-  }
-
-  if (SignalReason == FEXCore::Core::SignalEvent::Stop) {
-    // Our thread is stopping
-    // We don't care about anything at this point
-    // Set the stack to our starting location when we entered the core and get out safely
-    ArchHelpers::Context::SetSp(ucontext, Frame->ReturningStackLocation);
-
-    // Our ref counting doesn't matter anymore
-    Thread->CurrentFrame->SignalHandlerRefCounter = 0;
-
-    // Set the new PC
-    if (config.StaticRegisterAllocation && Thread->CPUBackend->IsAddressInCodeBuffer(ArchHelpers::Context::GetPc(ucontext))) {
-      // We are in jit, SRA must be spilled
-      ArchHelpers::Context::SetPc(ucontext, ThreadStopHandlerAddressSpillSRA);
-    } else {
-      if (config.StaticRegisterAllocation) {
-        // We are in non-jit, SRA is already spilled
-        LOGMAN_THROW_A_FMT(!IsAddressInDispatcher(ArchHelpers::Context::GetPc(ucontext)),
-                           "Signals in dispatcher have unsynchronized context");
-      }
-      ArchHelpers::Context::SetPc(ucontext, ThreadStopHandlerAddress);
-    }
-
-    // We need to be a little bit careful here
-    // If we were already paused (due to GDB) and we are immediately stopping (due to gdb kill)
-    // Then we need to ensure we don't double decrement our idle thread counter
-    if (Thread->RunningEvents.ThreadSleeping) {
-      // If the thread was sleeping then its idle counter was decremented
-      // Reincrement it here to not break logic
-      ++Thread->CTX->IdleWaitRefCount;
-    }
-
-    Thread->SignalReason.store(FEXCore::Core::SignalEvent::Nothing);
-    return true;
-  }
-
-  if (SignalReason == FEXCore::Core::SignalEvent::Return) {
-    RestoreThreadState(Thread, ucontext);
-
-    // Ref count our faults
-    // We use this to track if it is safe to clear cache
-    --Thread->CurrentFrame->SignalHandlerRefCounter;
-
-    Thread->SignalReason.store(FEXCore::Core::SignalEvent::Nothing);
-    return true;
-  }
-
-  return false;
-}
-
-uint64_t Dispatcher::GetCompileBlockPtr() {
-  using ClassPtrType = void (FEXCore::Context::Context::*)(FEXCore::Core::CpuStateFrame *, uint64_t);
-  union PtrCast {
-    ClassPtrType ClassPtr;
-    uintptr_t Data;
-  };
-
-  PtrCast CompileBlockPtr;
-  CompileBlockPtr.ClassPtr = &FEXCore::Context::Context::CompileBlockJit;
-  return CompileBlockPtr.Data;
-}
-
-}
@@ -1,28 +0,0 @@
-#pragma once
-
-#include "Interface/Core/Dispatcher/Dispatcher.h"
-
-#define XBYAK64
-#include <xbyak/xbyak.h>
-
-namespace FEXCore::Context {
-  struct Context;
-}
-
-namespace FEXCore::Core {
-  struct InternalThreadState;
-}
-
-namespace FEXCore::CPU {
-
-class X86Dispatcher final : public Dispatcher, public Xbyak::CodeGenerator {
-  public:
-    X86Dispatcher(FEXCore::Context::Context *ctx, const DispatcherConfig &config);
-    void InitThreadPointers(FEXCore::Core::InternalThreadState *Thread) override;
-    size_t GenerateGDBPauseCheck(uint8_t *CodeBuffer, uint64_t GuestRIP) override;
-    size_t GenerateInterpreterTrampoline(uint8_t *CodeBuffer) override;
-
-    virtual ~X86Dispatcher() override;
-};
-
-}
@@ -1,160 +0,0 @@
-#include "Interface/Core/CPUID.h"
-#include <FEXCore/Core/HostFeatures.h>
-
-#if defined(_M_ARM_64) || defined(VIXL_SIMULATOR)
-#include "aarch64/assembler-aarch64.h"
-#include "aarch64/cpu-aarch64.h"
-#include "aarch64/disasm-aarch64.h"
-#include "aarch64/assembler-aarch64.h"
-#endif
-
-#ifdef _M_X86_64
-#include <xbyak/xbyak_util.h>
-#endif
-
-namespace FEXCore {
-
-// Data Zero Prohibited flag
-// 0b0 = ZVA/GVA/GZVA permitted
-// 0b1 = ZVA/GVA/GZVA prohibited
-constexpr uint32_t DCZID_DZP_MASK = 0b1'0000;
-// Log2 of the blocksize in 32-bit words
-constexpr uint32_t DCZID_BS_MASK = 0b0'1111;
-
-#ifdef _M_ARM_64
-static uint32_t GetDCZID() {
-  uint64_t Result{};
-  __asm("mrs %[Res], DCZID_EL0"
-      : [Res] "=r" (Result));
-  return Result;
-}
-
-static uint32_t GetFPCR() {
-  uint64_t Result{};
-  __asm ("mrs %[Res], FPCR"
-    : [Res] "=r" (Result));
-  return Result;
-}
-
-static void SetFPCR(uint64_t Value) {
-  __asm ("msr FPCR, %[Value]"
-    :: [Value] "r" (Value));
-}
-
-#else
-static uint32_t GetDCZID() {
-  // Return unsupported
-  return DCZID_DZP_MASK;
-}
-#endif
-
-
-HostFeatures::HostFeatures() {
-#if defined(_M_ARM_64) || defined(VIXL_SIMULATOR)
-#ifdef VIXL_SIMULATOR
-  auto Features = vixl::CPUFeatures::All();
-#else
-  auto Features = vixl::CPUFeatures::InferFromOS();
-#endif
-  SupportsAES = Features.Has(vixl::CPUFeatures::Feature::kAES);
-  SupportsCRC = Features.Has(vixl::CPUFeatures::Feature::kCRC32);
-  SupportsAtomics = Features.Has(vixl::CPUFeatures::Feature::kAtomics);
-  SupportsRAND = Features.Has(vixl::CPUFeatures::Feature::kRNG);
-
-  // Only supported when FEAT_AFP is supported
-  SupportsFlushInputsToZero = Features.Has(vixl::CPUFeatures::Feature::kAFP);
-  SupportsRCPC = Features.Has(vixl::CPUFeatures::Feature::kRCpc);
-  SupportsTSOImm9 = Features.Has(vixl::CPUFeatures::Feature::kRCpcImm);
-
-  Supports3DNow = true;
-  SupportsSSE4A = true;
-#ifdef VIXL_SIMULATOR
-  // Hardcode enable SVE with 256-bit wide registers.
-  SupportsAVX = true;
-#else
-  SupportsAVX = Features.Has(vixl::CPUFeatures::Feature::kSVE2) &&
-                vixl::aarch64::CPU::ReadSVEVectorLengthInBits() >= 256;
-#endif
-  SupportsSHA = true;
-  SupportsBMI1 = true;
-  SupportsBMI2 = true;
-
-  if (!SupportsAtomics) {
-    WARN_ONCE_FMT("Host CPU doesn't support atomics. Expect bad performance");
-  }
-
-#ifdef _M_ARM_64
-  // We need to get the CPU's cache line size
-  // We expect sane targets that have correct cacheline sizes across clusters
-  uint64_t CTR;
-  __asm volatile ("mrs %[ctr], ctr_el0"
-    : [ctr] "=r"(CTR));
-
-  DCacheLineSize = 4 << ((CTR >> 16) & 0xF);
-  ICacheLineSize = 4 << (CTR & 0xF);
-
-  // Test if this CPU supports float exception trapping by attempting to enable
-  // On unsupported these bits are architecturally defined as RAZ/WI
-  constexpr uint32_t ExceptionEnableTraps =
-    (1U << 8) |  // Invalid Operation float exception trap enable
-    (1U << 9) |  // Divide by zero float exception trap enable
-    (1U << 10) | // Overflow float exception trap enable
-    (1U << 11) | // Underflow float exception trap enable
-    (1U << 12) | // Inexact float exception trap enable
-    (1U << 15);  // Input Denormal float exception trap enable
-
-  uint32_t OriginalFPCR = GetFPCR();
-  uint32_t FPCR = OriginalFPCR | ExceptionEnableTraps;
-  SetFPCR(FPCR);
-  FPCR = GetFPCR();
-  SupportsFloatExceptions = (FPCR & ExceptionEnableTraps) == ExceptionEnableTraps;
-
-  // Set FPCR back to original just in case anything changed
-  SetFPCR(OriginalFPCR);
-#endif
-
-#endif
-#if defined(_M_X86_64) && !defined(VIXL_SIMULATOR)
-  Xbyak::util::Cpu Features{};
-  SupportsAES = Features.has(Xbyak::util::Cpu::tAESNI);
-  SupportsCRC = Features.has(Xbyak::util::Cpu::tSSE42);
-  SupportsRAND = Features.has(Xbyak::util::Cpu::tRDRAND) && Features.has(Xbyak::util::Cpu::tRDSEED);
-  SupportsRCPC = true;
-  SupportsTSOImm9 = true;
-  Supports3DNow = Features.has(Xbyak::util::Cpu::t3DN) && Features.has(Xbyak::util::Cpu::tE3DN);
-  SupportsSSE4A = Features.has(Xbyak::util::Cpu::tSSE4a);
-  SupportsAVX = true;
-  SupportsSHA = Features.has(Xbyak::util::Cpu::tSHA);
-  SupportsBMI1 = Features.has(Xbyak::util::Cpu::tBMI1);
-  SupportsBMI2 = Features.has(Xbyak::util::Cpu::tBMI2);
-
-  // xbyak doesn't know how to check for CLZero
-  uint32_t eax, ebx, ecx, edx;
-  // First ensure we support a new enough extended CPUID function range
-  __cpuid(0x8000'0000, eax, ebx, ecx, edx);
-  if (eax >= 0x8000'0008U) {
-    // CLZero defined in 8000_00008_EBX[bit 0]
-    __cpuid(0x8000'0008, eax, ebx, ecx, edx);
-    SupportsCLZERO = ebx & 1;
-  }
-
-  SupportsFlushInputsToZero = true;
-  SupportsFloatExceptions = true;
-#endif
-
-#ifdef VIXL_SIMULATOR
-  // simulator doesn't support dc(ZVA)
-  SupportsCLZERO = false;
-#else
-  // Check if we can support cacheline clears
-  uint32_t DCZID = GetDCZID();
-  if ((DCZID & DCZID_DZP_MASK) == 0) {
-    uint32_t DCZID_Log2 = DCZID & DCZID_BS_MASK;
-    uint32_t DCZID_Bytes = (1 << DCZID_Log2) * sizeof(uint32_t);
-    // If the DC ZVA size matches the emulated cache line size
-    // This means we can use the instruction
-    SupportsCLZERO = DCZID_Bytes == CPUIDEmu::CACHELINE_SIZE;
-  }
-#endif
-}
-}
@@ -1,184 +0,0 @@
-#pragma once
-
-#include <FEXCore/IR/IR.h>
-
-#define GD *GetDest<uint64_t*>(Data->SSAData, Node)
-#define GDP GetDest<void*>(Data->SSAData, Node)
-
-#define DO_OP(size, type, func)              \
-  case size: {                                      \
-               auto *Dst_d  = reinterpret_cast<type*>(GDP);  \
-               auto *Src1_d = reinterpret_cast<type*>(Src1); \
-               auto *Src2_d = reinterpret_cast<type*>(Src2); \
-               *Dst_d = func(*Src1_d, *Src2_d);          \
-               break;                                            \
-             }
-#define DO_SCALAR_COMPARE_OP(size, type, type2, func)              \
-  case size: {                                      \
-  auto *Dst_d  = reinterpret_cast<type2*>(Tmp);  \
-  auto *Src1_d = reinterpret_cast<type*>(Src1); \
-  auto *Src2_d = reinterpret_cast<type*>(Src2); \
-  Dst_d[0] = func(Src1_d[0], Src2_d[0]);          \
-  break;                                            \
-  }
-
-#define DO_VECTOR_COMPARE_OP(size, type, type2, func)              \
-  case size: {                                      \
-  auto *Dst_d  = reinterpret_cast<type2*>(Tmp);  \
-  auto *Src1_d = reinterpret_cast<type*>(Src1); \
-  auto *Src2_d = reinterpret_cast<type*>(Src2); \
-  for (uint8_t i = 0; i < Elements; ++i) {          \
-    Dst_d[i] = func(Src1_d[i], Src2_d[i]);          \
-  }                                                 \
-  break;                                            \
-  }
-#define DO_VECTOR_OP(size, type, func)              \
-  case size: {                                      \
-  auto *Dst_d  = reinterpret_cast<type*>(Tmp);  \
-  auto *Src1_d = reinterpret_cast<type*>(Src1); \
-  auto *Src2_d = reinterpret_cast<type*>(Src2); \
-  for (uint8_t i = 0; i < Elements; ++i) {          \
-    Dst_d[i] = func(Src1_d[i], Src2_d[i]);          \
-  }                                                 \
-  break;                                            \
-  }
-#define DO_VECTOR_PAIR_OP(size, type, func)              \
-  case size: {                                      \
-  auto *Dst_d  = reinterpret_cast<type*>(Tmp);  \
-  auto *Src1_d = reinterpret_cast<type*>(Src1); \
-  auto *Src2_d = reinterpret_cast<type*>(Src2); \
-  for (uint8_t i = 0; i < Elements; ++i) {          \
-    Dst_d[i] = func(Src1_d[i*2], Src1_d[i*2 + 1]);          \
-    Dst_d[i+Elements] = func(Src2_d[i*2], Src2_d[i*2 + 1]);          \
-  }                                                 \
-  break;                                            \
-  }
-#define DO_VECTOR_SCALAR_OP(size, type, func)\
-  case size: {                                      \
-  auto *Dst_d  = reinterpret_cast<type*>(Tmp);  \
-  auto *Src1_d = reinterpret_cast<type*>(Src1); \
-  auto *Src2_d = reinterpret_cast<type*>(Src2); \
-  for (uint8_t i = 0; i < Elements; ++i) {          \
-    Dst_d[i] = func(Src1_d[i], *Src2_d);          \
-  }                                                 \
-  break;                                            \
-  }
-#define DO_VECTOR_0SRC_OP(size, type, func)              \
-  case size: {                                      \
-  auto *Dst_d  = reinterpret_cast<type*>(Tmp);  \
-  for (uint8_t i = 0; i < Elements; ++i) {          \
-    Dst_d[i] = func();          \
-  }                                                 \
-  break;                                            \
-  }
-#define DO_VECTOR_1SRC_OP(size, type, func)              \
-  case size: {                                      \
-  auto *Dst_d  = reinterpret_cast<type*>(Tmp);  \
-  auto *Src_d = reinterpret_cast<type*>(Src); \
-  for (uint8_t i = 0; i < Elements; ++i) {          \
-    Dst_d[i] = func(Src_d[i]);          \
-  }                                                 \
-  break;                                            \
-  }
-#define DO_VECTOR_REDUCE_1SRC_OP(size, type, func, start_val)              \
-  case size: {                                      \
-  auto *Dst_d  = reinterpret_cast<type*>(Tmp);  \
-  auto *Src_d = reinterpret_cast<type*>(Src); \
-  type begin = start_val;                           \
-  for (uint8_t i = 0; i < Elements; ++i) {          \
-    begin = func(begin, Src_d[i]);          \
-  }                                                 \
-  Dst_d[0] = begin;                                 \
-  break;                                            \
-  }
-#define DO_VECTOR_SAT_OP(size, type, func, min, max)              \
-  case size: {                                      \
-  auto *Dst_d  = reinterpret_cast<type*>(Tmp);  \
-  auto *Src1_d = reinterpret_cast<type*>(Src1); \
-  auto *Src2_d = reinterpret_cast<type*>(Src2); \
-  for (uint8_t i = 0; i < Elements; ++i) {          \
-    Dst_d[i] = func(Src1_d[i], Src2_d[i], min, max);          \
-  }                                                 \
-  break;                                            \
-  }
-
-#define DO_VECTOR_1SRC_2TYPE_OP(size, type, type2, func, min, max)              \
-  case size: {                                      \
-  auto *Dst_d  = reinterpret_cast<type*>(Tmp);  \
-  auto *Src_d = reinterpret_cast<type2*>(Src); \
-  for (uint8_t i = 0; i < Elements; ++i) {          \
-    Dst_d[i] = (type)func(Src_d[i], min, max);          \
-  }                                                 \
-  break;                                            \
-  }
-
-#define DO_VECTOR_1SRC_2TYPE_OP_NOSIZE(type, type2, func, min, max)              \
-  auto *Dst_d  = reinterpret_cast<type*>(Tmp);  \
-  auto *Src_d = reinterpret_cast<type2*>(Src); \
-  for (uint8_t i = 0; i < Elements; ++i) {          \
-    Dst_d[i] = (type)func(Src_d[i], min, max);          \
-  }
-#define DO_VECTOR_1SRC_2TYPE_OP_TOP(size, type, type2, func, min, max)              \
-  case size: {                                      \
-  auto *Dst_d  = reinterpret_cast<type*>(Tmp);  \
-  auto *Src_d = reinterpret_cast<type2*>(Src2); \
-  memcpy(Dst_d, Src1, Elements * sizeof(type2));\
-  for (uint8_t i = 0; i < Elements; ++i) {          \
-    Dst_d[i+Elements] = (type)func(Src_d[i], min, max);          \
-  }                                                 \
-  break;                                            \
-  }
-
-#define DO_VECTOR_1SRC_2TYPE_OP_TOP_SRC(size, type, type2, func, min, max)              \
-  case size: {                                      \
-  auto *Dst_d  = reinterpret_cast<type*>(Tmp);  \
-  auto *Src_d = reinterpret_cast<type2*>(Src); \
-  for (uint8_t i = 0; i < Elements; ++i) {          \
-    Dst_d[i] = (type)func(Src_d[i+Elements], min, max);          \
-  }                                                 \
-  break;                                            \
-  }
-#define DO_VECTOR_2SRC_2TYPE_OP(size, type, type2, func)              \
-  case size: {                                      \
-  auto *Dst_d  = reinterpret_cast<type*>(Tmp);  \
-  auto *Src1_d = reinterpret_cast<type2*>(Src1); \
-  auto *Src2_d = reinterpret_cast<type2*>(Src2); \
-  for (uint8_t i = 0; i < Elements; ++i) {          \
-    Dst_d[i] = (type)func((type)Src1_d[i], (type)Src2_d[i]);          \
-  }                                                 \
-  break;                                            \
-  }
-#define DO_VECTOR_2SRC_2TYPE_OP_TOP_SRC(size, type, type2, func)              \
-  case size: {                                      \
-  auto *Dst_d  = reinterpret_cast<type*>(Tmp);  \
-  auto *Src1_d = reinterpret_cast<type2*>(Src1); \
-  auto *Src2_d = reinterpret_cast<type2*>(Src2); \
-  for (uint8_t i = 0; i < Elements; ++i) {          \
-    Dst_d[i] = (type)func((type)Src1_d[i+Elements], (type)Src2_d[i+Elements]);          \
-  }                                                 \
-  break;                                            \
-  }
-
-struct InterpVector256 {
-  __uint128_t Lower;
-  __uint128_t Upper;
-};
-
-template<typename Res>
-Res GetDest(void* SSAData, FEXCore::IR::OrderedNodeWrapper Op) {
-  auto DstPtr = &reinterpret_cast<InterpVector256*>(SSAData)[Op.ID().Value];
-  return reinterpret_cast<Res>(DstPtr);
-}
-
-template<typename Res>
-Res GetDest(void* SSAData, FEXCore::IR::NodeID Op) {
-  auto DstPtr = &reinterpret_cast<InterpVector256*>(SSAData)[Op.Value];
-  return reinterpret_cast<Res>(DstPtr);
-}
-
-
-template<typename Res>
-Res GetSrc(void* SSAData, FEXCore::IR::OrderedNodeWrapper Src) {
-  auto DstPtr = &reinterpret_cast<InterpVector256*>(SSAData)[Src.ID().Value];
-  return reinterpret_cast<Res>(DstPtr);
-}
@@ -1,296 +0,0 @@
-/*
-$info$
-tags: backend|interpreter
-$end_info$
-*/
-
-#include "Interface/Core/CPUID.h"
-#include "Interface/Core/Interpreter/InterpreterClass.h"
-#include "Interface/Core/Interpreter/InterpreterOps.h"
-#include "Interface/Core/Interpreter/InterpreterDefines.h"
-
-#include <cstdint>
-
-namespace FEXCore::CPU {
-static inline void CacheLineFlush(char *Addr) {
-#ifdef _M_X86_64
-  __asm volatile (
-    "clflush (%[Addr]);"
-    :: [Addr] "r" (Addr)
-    : "memory");
-#else
-  __builtin___clear_cache(Addr, Addr+64);
-#endif
-}
-
-#define DEF_OP(x) void InterpreterOps::Op_##x(IR::IROp_Header *IROp, IROpData *Data, IR::NodeID Node)
-DEF_OP(LoadContext) {
-  const auto Op = IROp->C<IR::IROp_LoadContext>();
-  const auto OpSize = IROp->Size;
-
-  const auto ContextPtr = reinterpret_cast<uintptr_t>(Data->State->CurrentFrame);
-  const auto Src = ContextPtr + Op->Offset;
-
-  #define LOAD_CTX(x, y) \
-    case x: { \
-      y const *MemData = reinterpret_cast<y const*>(Src); \
-      GD = *MemData; \
-      break; \
-    }
-
-  switch (OpSize) {
-    LOAD_CTX(1, uint8_t)
-    LOAD_CTX(2, uint16_t)
-    LOAD_CTX(4, uint32_t)
-    LOAD_CTX(8, uint64_t)
-    case 16:
-    case 32: {
-      void const *MemData = reinterpret_cast<void const*>(Src);
-      memcpy(GDP, MemData, OpSize);
-      break;
-    }
-    default:
-      LOGMAN_MSG_A_FMT("Unhandled LoadContext size: {}", OpSize);
-      break;
-  }
-  #undef LOAD_CTX
-}
-
-DEF_OP(StoreContext) {
-  const auto Op = IROp->C<IR::IROp_StoreContext>();
-  const auto OpSize = IROp->Size;
-
-  const auto ContextPtr = reinterpret_cast<uintptr_t>(Data->State->CurrentFrame);
-  const auto Dst = ContextPtr + Op->Offset;
-
-  void *MemData = reinterpret_cast<void*>(Dst);
-  void *Src = GetSrc<void*>(Data->SSAData, Op->Value);
-  memcpy(MemData, Src, OpSize);
-}
-
-DEF_OP(LoadRegister) {
-  LOGMAN_MSG_A_FMT("Unimplemented");
-}
-
-DEF_OP(StoreRegister) {
-  LOGMAN_MSG_A_FMT("Unimplemented");
-}
-
-DEF_OP(LoadContextIndexed) {
-  const auto Op = IROp->C<IR::IROp_LoadContextIndexed>();
-  const auto OpSize = IROp->Size;
-
-  const auto Index = *GetSrc<uint64_t*>(Data->SSAData, Op->Index);
-
-  const auto ContextPtr = reinterpret_cast<uintptr_t>(Data->State->CurrentFrame);
-  const auto Src = ContextPtr + Op->BaseOffset + (Index * Op->Stride);
-
-  #define LOAD_CTX(x, y) \
-    case x: { \
-      y const *MemData = reinterpret_cast<y const*>(Src); \
-      GD = *MemData; \
-      break; \
-    }
-
-  switch (OpSize) {
-    LOAD_CTX(1, uint8_t)
-    LOAD_CTX(2, uint16_t)
-    LOAD_CTX(4, uint32_t)
-    LOAD_CTX(8, uint64_t)
-    case 16:
-    case 32: {
-      void const *MemData = reinterpret_cast<void const*>(Src);
-      memcpy(GDP, MemData, OpSize);
-      break;
-    }
-    default:
-      LOGMAN_MSG_A_FMT("Unhandled LoadContextIndexed size: {}", OpSize);
-      break;
-  }
-  #undef LOAD_CTX
-}
-
-DEF_OP(StoreContextIndexed) {
-  const auto Op = IROp->C<IR::IROp_StoreContextIndexed>();
-  const auto OpSize = IROp->Size;
-
-  const auto Index = *GetSrc<uint64_t*>(Data->SSAData, Op->Index);
-
-  const auto ContextPtr = reinterpret_cast<uintptr_t>(Data->State->CurrentFrame);
-  const auto Dst = ContextPtr + Op->BaseOffset + (Index * Op->Stride);
-
-  void *MemData = reinterpret_cast<void*>(Dst);
-  void *Src = GetSrc<void*>(Data->SSAData, Op->Value);
-  memcpy(MemData, Src, OpSize);
-}
-
-DEF_OP(SpillRegister) {
-  LOGMAN_MSG_A_FMT("Unimplemented");
-}
-
-DEF_OP(FillRegister) {
-  LOGMAN_MSG_A_FMT("Unimplemented");
-}
-
-DEF_OP(LoadFlag) {
-  auto Op = IROp->C<IR::IROp_LoadFlag>();
-
-  uintptr_t ContextPtr = reinterpret_cast<uintptr_t>(Data->State->CurrentFrame);
-  ContextPtr += offsetof(FEXCore::Core::CPUState, flags[0]);
-  ContextPtr += Op->Flag;
-  uint8_t const *MemData = reinterpret_cast<uint8_t const*>(ContextPtr);
-  GD = *MemData;
-}
-
-DEF_OP(StoreFlag) {
-  auto Op = IROp->C<IR::IROp_StoreFlag>();
-  uint8_t Arg = *GetSrc<uint8_t*>(Data->SSAData, Op->Value);
-
-  uintptr_t ContextPtr = reinterpret_cast<uintptr_t>(Data->State->CurrentFrame);
-  ContextPtr += offsetof(FEXCore::Core::CPUState, flags[0]);
-  ContextPtr += Op->Flag;
-  uint8_t *MemData = reinterpret_cast<uint8_t*>(ContextPtr);
-  *MemData = Arg;
-}
-
-DEF_OP(LoadMem) {
-  const auto Op = IROp->C<IR::IROp_LoadMem>();
-  const auto OpSize = IROp->Size;
-
-  uint8_t const *MemData = *GetSrc<uint8_t const**>(Data->SSAData, Op->Addr);
-
-  if (!Op->Offset.IsInvalid()) {
-    auto Offset = *GetSrc<uintptr_t const*>(Data->SSAData, Op->Offset) * Op->OffsetScale;
-
-    switch(Op->OffsetType.Val) {
-      case IR::MEM_OFFSET_SXTX.Val: MemData +=  Offset; break;
-      case IR::MEM_OFFSET_UXTW.Val: MemData += (uint32_t)Offset; break;
-      case IR::MEM_OFFSET_SXTW.Val: MemData += (int32_t)Offset; break;
-    }
-  }
-
-  memset(GDP, 0, Core::CPUState::XMM_AVX_REG_SIZE);
-  switch (OpSize) {
-    case 1: {
-      auto D = reinterpret_cast<const std::atomic<uint8_t>*>(MemData);
-      GD = D->load();
-      break;
-    }
-    case 2: {
-      auto D = reinterpret_cast<const std::atomic<uint16_t>*>(MemData);
-      GD = D->load();
-      break;
-    }
-    case 4: {
-      auto D = reinterpret_cast<const std::atomic<uint32_t>*>(MemData);
-      GD = D->load();
-      break;
-    }
-    case 8: {
-      auto D = reinterpret_cast<const std::atomic<uint64_t>*>(MemData);
-      GD = D->load();
-      break;
-    }
-    default:
-      memcpy(GDP, MemData, OpSize);
-      break;
-  }
-}
-
-DEF_OP(StoreMem) {
-  const auto Op = IROp->C<IR::IROp_StoreMem>();
-  const auto OpSize = IROp->Size;
-
-  uint8_t *MemData = *GetSrc<uint8_t **>(Data->SSAData, Op->Addr);
-
-  if (!Op->Offset.IsInvalid()) {
-    auto Offset = *GetSrc<uintptr_t const*>(Data->SSAData, Op->Offset) * Op->OffsetScale;
-
-    switch(Op->OffsetType.Val) {
-      case IR::MEM_OFFSET_SXTX.Val: MemData +=  Offset; break;
-      case IR::MEM_OFFSET_UXTW.Val: MemData += (uint32_t)Offset; break;
-      case IR::MEM_OFFSET_SXTW.Val: MemData += (int32_t)Offset; break;
-    }
-  }
-  switch (OpSize) {
-    case 1: {
-      reinterpret_cast<std::atomic<uint8_t>*>(MemData)->store(*GetSrc<uint8_t*>(Data->SSAData, Op->Value));
-      break;
-    }
-    case 2: {
-      reinterpret_cast<std::atomic<uint16_t>*>(MemData)->store(*GetSrc<uint16_t*>(Data->SSAData, Op->Value));
-      break;
-    }
-    case 4: {
-      reinterpret_cast<std::atomic<uint32_t>*>(MemData)->store(*GetSrc<uint32_t*>(Data->SSAData, Op->Value));
-      break;
-    }
-    case 8: {
-      reinterpret_cast<std::atomic<uint64_t>*>(MemData)->store(*GetSrc<uint64_t*>(Data->SSAData, Op->Value));
-      break;
-    }
-
-    default:
-      memcpy(MemData, GetSrc<void*>(Data->SSAData, Op->Value), OpSize);
-      break;
-  }
-}
-
-DEF_OP(VLoadMemElement) {
-  auto Op = IROp->C<IR::IROp_VLoadMemElement>();
-  void const *MemData = *GetSrc<void const**>(Data->SSAData, Op->Value);
-
-  memcpy(GDP, GetSrc<void*>(Data->SSAData, Op->Addr), 16);
-  memcpy(reinterpret_cast<void*>(reinterpret_cast<uintptr_t>(GDP) + (Op->Header.ElementSize * Op->Index)),
-    MemData, Op->Header.ElementSize);
-}
-
-DEF_OP(VStoreMemElement) {
-  #define STORE_DATA(x, y) \
-    case x: { \
-      y *MemData = *GetSrc<y**>(Data->SSAData, Op->Value); \
-      memcpy(MemData, &GetSrc<y*>(Data->SSAData, Op->Addr)[Op->Index], sizeof(y)); \
-      break; \
-    }
-
-  auto Op = IROp->C<IR::IROp_VStoreMemElement>();
-  uint8_t OpSize = IROp->Size;
-
-  switch (OpSize) {
-    STORE_DATA(1, uint8_t)
-    STORE_DATA(2, uint16_t)
-    STORE_DATA(4, uint32_t)
-    STORE_DATA(8, uint64_t)
-    default: LOGMAN_MSG_A_FMT("Unhandled StoreMem size"); break;
-  }
-  #undef STORE_DATA
-}
-
-DEF_OP(CacheLineClear) {
-  auto Op = IROp->C<IR::IROp_CacheLineClear>();
-
-  char *MemData = *GetSrc<char **>(Data->SSAData, Op->Addr);
-
-  // 64-byte cache line clear
-  CacheLineFlush(MemData);
-}
-
-DEF_OP(CacheLineZero) {
-  auto Op = IROp->C<IR::IROp_CacheLineZero>();
-
-  uintptr_t MemData = *GetSrc<uintptr_t*>(Data->SSAData, Op->Addr);
-
-  // Force cacheline alignment
-  MemData = MemData & ~(CPUIDEmu::CACHELINE_SIZE - 1);
-
-  using DataType = uint64_t;
-  DataType *MemData64 = reinterpret_cast<DataType*>(MemData);
-
-  // 64-byte cache line zero
-  for (size_t i = 0; i < (CPUIDEmu::CACHELINE_SIZE / sizeof(DataType)); ++i) {
-    MemData64[i] = 0;
-  }
-}
-
-#undef DEF_OP
-} // namespace FEXCore::CPU
@@ -1,941 +0,0 @@
-/*
-$info$
-tags: backend|arm64
-$end_info$
-*/
-
-#include "Interface/Context/Context.h"
-#include "Interface/Core/JIT/Arm64/JITClass.h"
-
-namespace FEXCore::CPU {
-using namespace vixl;
-using namespace vixl::aarch64;
-#define DEF_OP(x) void Arm64JITCore::Op_##x(IR::IROp_Header *IROp, IR::NodeID Node)
-DEF_OP(CASPair) {
-  auto Op = IROp->C<IR::IROp_CASPair>();
-  // Size is the size of each pair element
-  auto Dst = GetSrcPair<RA_64>(Node);
-  auto Expected = GetSrcPair<RA_64>(Op->Expected.ID());
-  auto Desired = GetSrcPair<RA_64>(Op->Desired.ID());
-  auto MemSrc = GetReg<RA_64>(Op->Addr.ID());
-
-  if (CTX->HostFeatures.SupportsAtomics) {
-    mov(TMP3, Expected.first);
-    mov(TMP4, Expected.second);
-
-    switch (IROp->ElementSize) {
-    case 4:
-      caspal(TMP3.W(), TMP4.W(), Desired.first.W(), Desired.second.W(), MemOperand(MemSrc));
-      mov(Dst.first.W(), TMP3.W());
-      mov(Dst.second.W(), TMP4.W());
-      break;
-    case 8:
-      caspal(TMP3.X(), TMP4.X(), Desired.first.X(), Desired.second.X(), MemOperand(MemSrc));
-      mov(Dst.first, TMP3);
-      mov(Dst.second, TMP4);
-      break;
-    default: LOGMAN_MSG_A_FMT("Unsupported: {}", IROp->ElementSize);
-    }
-  }
-  else {
-    switch (IROp->ElementSize) {
-      case 4: {
-        aarch64::Label LoopTop;
-        aarch64::Label LoopNotExpected;
-        aarch64::Label LoopExpected;
-        bind(&LoopTop);
-
-        ldaxp(TMP2.W(), TMP3.W(), MemOperand(MemSrc));
-        cmp(TMP2.W(), Expected.first.W());
-        ccmp(TMP3.W(), Expected.second.W(), NoFlag, Condition::eq);
-        b(&LoopNotExpected, Condition::ne);
-        stlxp(TMP2.W(), Desired.first.W(), Desired.second.W(), MemOperand(MemSrc));
-        cbnz(TMP2.W(), &LoopTop);
-        mov(Dst.first.W(), Expected.first.W());
-        mov(Dst.second.W(), Expected.second.W());
-
-        b(&LoopExpected);
-
-          bind(&LoopNotExpected);
-          mov(Dst.first.W(), TMP2.W());
-          mov(Dst.second.W(), TMP3.W());
-          // exclusive monitor needs to be cleared here
-          // Might have hit the case where ldaxr was hit but stlxr wasn't
-          clrex();
-        bind(&LoopExpected);
-        break;
-      }
-      case 8: {
-        aarch64::Label LoopTop;
-        aarch64::Label LoopNotExpected;
-        aarch64::Label LoopExpected;
-        bind(&LoopTop);
-
-        ldaxp(TMP2.X(), TMP3.X(), MemOperand(MemSrc));
-        cmp(TMP2.X(), Expected.first.X());
-        ccmp(TMP3.X(), Expected.second.X(), NoFlag, Condition::eq);
-        b(&LoopNotExpected, Condition::ne);
-        stlxp(TMP2.X(), Desired.first.X(), Desired.second.X(), MemOperand(MemSrc));
-        cbnz(TMP2.X(), &LoopTop);
-        mov(Dst.first.X(), Expected.first.X());
-        mov(Dst.second.X(), Expected.second.X());
-
-        b(&LoopExpected);
-
-          bind(&LoopNotExpected);
-          mov(Dst.first.X(), TMP2.X());
-          mov(Dst.second.X(), TMP3.X());
-          // exclusive monitor needs to be cleared here
-          // Might have hit the case where ldaxr was hit but stlxr wasn't
-          clrex();
-        bind(&LoopExpected);
-        break;
-      }
-      default: LOGMAN_MSG_A_FMT("Unsupported: {}", IROp->ElementSize);
-    }
-  }
-}
-
-DEF_OP(CAS) {
-  auto Op = IROp->C<IR::IROp_CAS>();
-  uint8_t OpSize = IROp->Size;
-  // DataSrc = *Src1
-  // if (DataSrc == Src3) { *Src1 == Src2; } Src2 = DataSrc
-  // This will write to memory! Careful!
-
-  auto Expected = GetReg<RA_64>(Op->Expected.ID());
-  auto Desired = GetReg<RA_64>(Op->Desired.ID());
-  auto MemSrc = GetReg<RA_64>(Op->Addr.ID());
-
-  if (CTX->HostFeatures.SupportsAtomics) {
-    mov(TMP2, Expected);
-    switch (OpSize) {
-    case 1: casalb(TMP2.W(), Desired.W(), MemOperand(MemSrc)); break;
-    case 2: casalh(TMP2.W(), Desired.W(), MemOperand(MemSrc)); break;
-    case 4: casal(TMP2.W(), Desired.W(), MemOperand(MemSrc)); break;
-    case 8: casal(TMP2.X(), Desired.X(), MemOperand(MemSrc)); break;
-    default: LOGMAN_MSG_A_FMT("Unsupported: {}", OpSize);
-    }
-    mov(GetReg<RA_64>(Node), TMP2);
-  }
-  else {
-    switch (OpSize) {
-      case 1: {
-        aarch64::Label LoopTop;
-        aarch64::Label LoopNotExpected;
-        aarch64::Label LoopExpected;
-        bind(&LoopTop);
-        ldaxrb(TMP2.W(), MemOperand(MemSrc));
-        cmp(TMP2.W(), Operand(Expected.W(), Extend::UXTB));
-        b(&LoopNotExpected, Condition::ne);
-        stlxrb(TMP3.W(), Desired.W(), MemOperand(MemSrc));
-        cbnz(TMP3.W(), &LoopTop);
-        mov(GetReg<RA_32>(Node), Expected.W());
-        b(&LoopExpected);
-
-          bind(&LoopNotExpected);
-          mov(GetReg<RA_32>(Node), TMP2.W());
-          // exclusive monitor needs to be cleared here
-          // Might have hit the case where ldaxr was hit but stlxr wasn't
-          clrex();
-        bind(&LoopExpected);
-        break;
-      }
-      case 2: {
-        aarch64::Label LoopTop;
-        aarch64::Label LoopNotExpected;
-        aarch64::Label LoopExpected;
-        bind(&LoopTop);
-        ldaxrh(TMP2.W(), MemOperand(MemSrc));
-        cmp(TMP2.W(), Operand(Expected.W(), Extend::UXTH));
-        b(&LoopNotExpected, Condition::ne);
-        stlxrh(TMP3.W(), Desired.W(), MemOperand(MemSrc));
-        cbnz(TMP3.W(), &LoopTop);
-        mov(GetReg<RA_32>(Node), Expected.W());
-        b(&LoopExpected);
-
-          bind(&LoopNotExpected);
-          mov(GetReg<RA_32>(Node), TMP2.W());
-          // exclusive monitor needs to be cleared here
-          // Might have hit the case where ldaxr was hit but stlxr wasn't
-          clrex();
-        bind(&LoopExpected);
-        break;
-      }
-      case 4: {
-        aarch64::Label LoopTop;
-        aarch64::Label LoopNotExpected;
-        aarch64::Label LoopExpected;
-        bind(&LoopTop);
-        ldaxr(TMP2.W(), MemOperand(MemSrc));
-        cmp(TMP2.W(), Expected.W());
-        b(&LoopNotExpected, Condition::ne);
-        stlxr(TMP3.W(), Desired.W(), MemOperand(MemSrc));
-        cbnz(TMP3.W(), &LoopTop);
-        mov(GetReg<RA_32>(Node), Expected.W());
-        b(&LoopExpected);
-
-          bind(&LoopNotExpected);
-          mov(GetReg<RA_32>(Node), TMP2.W());
-          // exclusive monitor needs to be cleared here
-          // Might have hit the case where ldaxr was hit but stlxr wasn't
-          clrex();
-        bind(&LoopExpected);
-        break;
-      }
-      case 8: {
-        aarch64::Label LoopTop;
-        aarch64::Label LoopNotExpected;
-        aarch64::Label LoopExpected;
-        bind(&LoopTop);
-        ldaxr(TMP2, MemOperand(MemSrc));
-        cmp(TMP2, Expected);
-        b(&LoopNotExpected, Condition::ne);
-        stlxr(TMP2, Desired, MemOperand(MemSrc));
-        cbnz(TMP2, &LoopTop);
-        mov(GetReg<RA_64>(Node), Expected);
-        b(&LoopExpected);
-
-          bind(&LoopNotExpected);
-          mov(GetReg<RA_64>(Node), TMP2);
-          // exclusive monitor needs to be cleared here
-          // Might have hit the case where ldaxr was hit but stlxr wasn't
-          clrex();
-        bind(&LoopExpected);
-
-        break;
-      }
-      default:  LOGMAN_MSG_A_FMT("Unhandled Atomic size: {}", OpSize);
-    }
-  }
-}
-
-DEF_OP(AtomicAdd) {
-  auto Op = IROp->C<IR::IROp_AtomicAdd>();
-
-  auto MemSrc = GetReg<RA_64>(Op->Addr.ID());
-
-  if (CTX->HostFeatures.SupportsAtomics) {
-    switch (IROp->Size) {
-    case 1: staddlb(GetReg<RA_32>(Op->Value.ID()), MemOperand(MemSrc)); break;
-    case 2: staddlh(GetReg<RA_32>(Op->Value.ID()), MemOperand(MemSrc)); break;
-    case 4: staddl(GetReg<RA_32>(Op->Value.ID()), MemOperand(MemSrc)); break;
-    case 8: staddl(GetReg<RA_64>(Op->Value.ID()), MemOperand(MemSrc)); break;
-    default:  LOGMAN_MSG_A_FMT("Unhandled Atomic size: {}", IROp->Size);
-    }
-  }
-  else {
-    // TMP2-TMP3
-    switch (IROp->Size) {
-      case 1: {
-        aarch64::Label LoopTop;
-        bind(&LoopTop);
-        ldaxrb(TMP2.W(), MemOperand(MemSrc));
-        add(TMP2.W(), TMP2.W(), GetReg<RA_32>(Op->Value.ID()));
-        stlxrb(TMP2.W(), TMP2.W(), MemOperand(MemSrc));
-        cbnz(TMP2.W(), &LoopTop);
-        break;
-      }
-      case 2: {
-        aarch64::Label LoopTop;
-        bind(&LoopTop);
-        ldaxrh(TMP2.W(), MemOperand(MemSrc));
-        add(TMP2.W(), TMP2.W(), GetReg<RA_32>(Op->Value.ID()));
-        stlxrh(TMP2.W(), TMP2.W(), MemOperand(MemSrc));
-        cbnz(TMP2.W(), &LoopTop);
-        break;
-      }
-      case 4: {
-        aarch64::Label LoopTop;
-        bind(&LoopTop);
-        ldaxr(TMP2.W(), MemOperand(MemSrc));
-        add(TMP2.W(), TMP2.W(), GetReg<RA_32>(Op->Value.ID()));
-        stlxr(TMP2.W(), TMP2.W(), MemOperand(MemSrc));
-        cbnz(TMP2.W(), &LoopTop);
-        break;
-      }
-      case 8: {
-        aarch64::Label LoopTop;
-        bind(&LoopTop);
-        ldaxr(TMP2, MemOperand(MemSrc));
-        add(TMP2, TMP2, GetReg<RA_64>(Op->Value.ID()));
-        stlxr(TMP2, TMP2, MemOperand(MemSrc));
-        cbnz(TMP2, &LoopTop);
-        break;
-      }
-      default:  LOGMAN_MSG_A_FMT("Unhandled Atomic size: {}", IROp->Size);
-    }
-  }
-}
-
-DEF_OP(AtomicSub) {
-  auto Op = IROp->C<IR::IROp_AtomicSub>();
-
-  auto MemSrc = GetReg<RA_64>(Op->Addr.ID());
-
-  if (CTX->HostFeatures.SupportsAtomics) {
-    neg(TMP2, GetReg<RA_64>(Op->Value.ID()));
-    switch (IROp->Size) {
-    case 1: staddlb(TMP2.W(), MemOperand(MemSrc)); break;
-    case 2: staddlh(TMP2.W(), MemOperand(MemSrc)); break;
-    case 4: staddl(TMP2.W(), MemOperand(MemSrc)); break;
-    case 8: staddl(TMP2.X(), MemOperand(MemSrc)); break;
-    default:  LOGMAN_MSG_A_FMT("Unhandled Atomic size: {}", IROp->Size);
-    }
-  }
-  else {
-    // TMP2-TMP3
-    switch (IROp->Size) {
-      case 1: {
-        aarch64::Label LoopTop;
-        bind(&LoopTop);
-        ldaxrb(TMP2.W(), MemOperand(MemSrc));
-        sub(TMP2.W(), TMP2.W(), GetReg<RA_32>(Op->Value.ID()));
-        stlxrb(TMP2.W(), TMP2.W(), MemOperand(MemSrc));
-        cbnz(TMP2.W(), &LoopTop);
-        break;
-      }
-      case 2: {
-        aarch64::Label LoopTop;
-        bind(&LoopTop);
-        ldaxrh(TMP2.W(), MemOperand(MemSrc));
-        sub(TMP2.W(), TMP2.W(), GetReg<RA_32>(Op->Value.ID()));
-        stlxrh(TMP2.W(), TMP2.W(), MemOperand(MemSrc));
-        cbnz(TMP2.W(), &LoopTop);
-        break;
-      }
-      case 4: {
-        aarch64::Label LoopTop;
-        bind(&LoopTop);
-        ldaxr(TMP2.W(), MemOperand(MemSrc));
-        sub(TMP2.W(), TMP2.W(), GetReg<RA_32>(Op->Value.ID()));
-        stlxr(TMP2.W(), TMP2.W(), MemOperand(MemSrc));
-        cbnz(TMP2.W(), &LoopTop);
-        break;
-      }
-      case 8: {
-        aarch64::Label LoopTop;
-        bind(&LoopTop);
-        ldaxr(TMP2, MemOperand(MemSrc));
-        sub(TMP2, TMP2, GetReg<RA_64>(Op->Value.ID()));
-        stlxr(TMP2, TMP2, MemOperand(MemSrc));
-        cbnz(TMP2, &LoopTop);
-        break;
-      }
-      default:  LOGMAN_MSG_A_FMT("Unhandled Atomic size: {}", IROp->Size);
-    }
-  }
-}
-
-DEF_OP(AtomicAnd) {
-  auto Op = IROp->C<IR::IROp_AtomicAnd>();
-
-  auto MemSrc = GetReg<RA_64>(Op->Addr.ID());
-
-  if (CTX->HostFeatures.SupportsAtomics) {
-    mvn(TMP2, GetReg<RA_64>(Op->Value.ID()));
-    switch (IROp->Size) {
-    case 1: stclrlb(TMP2.W(), MemOperand(MemSrc)); break;
-    case 2: stclrlh(TMP2.W(), MemOperand(MemSrc)); break;
-    case 4: stclrl(TMP2.W(), MemOperand(MemSrc)); break;
-    case 8: stclrl(TMP2.X(), MemOperand(MemSrc)); break;
-    default:  LOGMAN_MSG_A_FMT("Unhandled Atomic size: {}", IROp->Size);
-    }
-  }
-  else {
-    // TMP2-TMP3
-    switch (IROp->Size) {
-      case 1: {
-        aarch64::Label LoopTop;
-        bind(&LoopTop);
-        ldaxrb(TMP2.W(), MemOperand(MemSrc));
-        and_(TMP2.W(), TMP2.W(), GetReg<RA_32>(Op->Value.ID()));
-        stlxrb(TMP2.W(), TMP2.W(), MemOperand(MemSrc));
-        cbnz(TMP2.W(), &LoopTop);
-        break;
-      }
-      case 2: {
-        aarch64::Label LoopTop;
-        bind(&LoopTop);
-        ldaxrh(TMP2.W(), MemOperand(MemSrc));
-        and_(TMP2.W(), TMP2.W(), GetReg<RA_32>(Op->Value.ID()));
-        stlxrh(TMP2.W(), TMP2.W(), MemOperand(MemSrc));
-        cbnz(TMP2.W(), &LoopTop);
-        break;
-      }
-      case 4: {
-        aarch64::Label LoopTop;
-        bind(&LoopTop);
-        ldaxr(TMP2.W(), MemOperand(MemSrc));
-        and_(TMP2.W(), TMP2.W(), GetReg<RA_32>(Op->Value.ID()));
-        stlxr(TMP2.W(), TMP2.W(), MemOperand(MemSrc));
-        cbnz(TMP2.W(), &LoopTop);
-        break;
-      }
-      case 8: {
-        aarch64::Label LoopTop;
-        bind(&LoopTop);
-        ldaxr(TMP2, MemOperand(MemSrc));
-        and_(TMP2, TMP2, GetReg<RA_64>(Op->Value.ID()));
-        stlxr(TMP2, TMP2, MemOperand(MemSrc));
-        cbnz(TMP2, &LoopTop);
-        break;
-      }
-      default:  LOGMAN_MSG_A_FMT("Unhandled Atomic size: {}", IROp->Size);
-    }
-  }
-}
-
-DEF_OP(AtomicOr) {
-  auto Op = IROp->C<IR::IROp_AtomicOr>();
-
-  auto MemSrc = GetReg<RA_64>(Op->Addr.ID());
-
-  if (CTX->HostFeatures.SupportsAtomics) {
-    switch (IROp->Size) {
-    case 1: stsetlb(GetReg<RA_32>(Op->Value.ID()), MemOperand(MemSrc)); break;
-    case 2: stsetlh(GetReg<RA_32>(Op->Value.ID()), MemOperand(MemSrc)); break;
-    case 4: stsetl(GetReg<RA_32>(Op->Value.ID()), MemOperand(MemSrc)); break;
-    case 8: stsetl(GetReg<RA_64>(Op->Value.ID()), MemOperand(MemSrc)); break;
-    default:  LOGMAN_MSG_A_FMT("Unhandled Atomic size: {}", IROp->Size);
-    }
-  }
-  else {
-    // TMP2-TMP3
-    switch (IROp->Size) {
-      case 1: {
-        aarch64::Label LoopTop;
-        bind(&LoopTop);
-        ldaxrb(TMP2.W(), MemOperand(MemSrc));
-        orr(TMP2.W(), TMP2.W(), GetReg<RA_32>(Op->Value.ID()));
-        stlxrb(TMP2.W(), TMP2.W(), MemOperand(MemSrc));
-        cbnz(TMP2.W(), &LoopTop);
-        break;
-      }
-      case 2: {
-        aarch64::Label LoopTop;
-        bind(&LoopTop);
-        ldaxrh(TMP2.W(), MemOperand(MemSrc));
-        orr(TMP2.W(), TMP2.W(), GetReg<RA_32>(Op->Value.ID()));
-        stlxrh(TMP2.W(), TMP2.W(), MemOperand(MemSrc));
-        cbnz(TMP2.W(), &LoopTop);
-        break;
-      }
-      case 4: {
-        aarch64::Label LoopTop;
-        bind(&LoopTop);
-        ldaxr(TMP2.W(), MemOperand(MemSrc));
-        orr(TMP2.W(), TMP2.W(), GetReg<RA_32>(Op->Value.ID()));
-        stlxr(TMP2.W(), TMP2.W(), MemOperand(MemSrc));
-        cbnz(TMP2.W(), &LoopTop);
-        break;
-      }
-      case 8: {
-        aarch64::Label LoopTop;
-        bind(&LoopTop);
-        ldaxr(TMP2, MemOperand(MemSrc));
-        orr(TMP2, TMP2, GetReg<RA_64>(Op->Value.ID()));
-        stlxr(TMP2, TMP2, MemOperand(MemSrc));
-        cbnz(TMP2, &LoopTop);
-        break;
-      }
-      default:  LOGMAN_MSG_A_FMT("Unhandled Atomic size: {}", IROp->Size);
-    }
-  }
-}
-
-DEF_OP(AtomicXor) {
-  auto Op = IROp->C<IR::IROp_AtomicXor>();
-
-  auto MemSrc = GetReg<RA_64>(Op->Addr.ID());
-
-  if (CTX->HostFeatures.SupportsAtomics) {
-    switch (IROp->Size) {
-    case 1: steorlb(GetReg<RA_32>(Op->Value.ID()), MemOperand(MemSrc)); break;
-    case 2: steorlh(GetReg<RA_32>(Op->Value.ID()), MemOperand(MemSrc)); break;
-    case 4: steorl(GetReg<RA_32>(Op->Value.ID()), MemOperand(MemSrc)); break;
-    case 8: steorl(GetReg<RA_64>(Op->Value.ID()), MemOperand(MemSrc)); break;
-    default:  LOGMAN_MSG_A_FMT("Unhandled Atomic size: {}", IROp->Size);
-    }
-  }
-  else {
-    // TMP2-TMP3
-    switch (IROp->Size) {
-      case 1: {
-        aarch64::Label LoopTop;
-        bind(&LoopTop);
-        ldaxrb(TMP2.W(), MemOperand(MemSrc));
-        eor(TMP2.W(), TMP2.W(), GetReg<RA_32>(Op->Value.ID()));
-        stlxrb(TMP2.W(), TMP2.W(), MemOperand(MemSrc));
-        cbnz(TMP2.W(), &LoopTop);
-        break;
-      }
-      case 2: {
-        aarch64::Label LoopTop;
-        bind(&LoopTop);
-        ldaxrh(TMP2.W(), MemOperand(MemSrc));
-        eor(TMP2.W(), TMP2.W(), GetReg<RA_32>(Op->Value.ID()));
-        stlxrh(TMP2.W(), TMP2.W(), MemOperand(MemSrc));
-        cbnz(TMP2.W(), &LoopTop);
-        break;
-      }
-      case 4: {
-        aarch64::Label LoopTop;
-        bind(&LoopTop);
-        ldaxr(TMP2.W(), MemOperand(MemSrc));
-        eor(TMP2.W(), TMP2.W(), GetReg<RA_32>(Op->Value.ID()));
-        stlxr(TMP2.W(), TMP2.W(), MemOperand(MemSrc));
-        cbnz(TMP2.W(), &LoopTop);
-        break;
-      }
-      case 8: {
-        aarch64::Label LoopTop;
-        bind(&LoopTop);
-        ldaxr(TMP2, MemOperand(MemSrc));
-        eor(TMP2, TMP2, GetReg<RA_64>(Op->Value.ID()));
-        stlxr(TMP2, TMP2, MemOperand(MemSrc));
-        cbnz(TMP2, &LoopTop);
-        break;
-      }
-      default:  LOGMAN_MSG_A_FMT("Unhandled Atomic size: {}", IROp->Size);
-    }
-  }
-}
-
-DEF_OP(AtomicSwap) {
-  auto Op = IROp->C<IR::IROp_AtomicSwap>();
-
-  auto MemSrc = GetReg<RA_64>(Op->Addr.ID());
-
-  if (CTX->HostFeatures.SupportsAtomics) {
-    mov(TMP2, GetReg<RA_64>(Op->Value.ID()));
-    switch (IROp->Size) {
-    case 1: swpalb(TMP2.W(), GetReg<RA_32>(Node), MemOperand(MemSrc)); break;
-    case 2: swpalh(TMP2.W(), GetReg<RA_32>(Node), MemOperand(MemSrc)); break;
-    case 4: swpal(TMP2.W(), GetReg<RA_32>(Node), MemOperand(MemSrc)); break;
-    case 8: swpal(TMP2.X(), GetReg<RA_64>(Node), MemOperand(MemSrc)); break;
-    default:  LOGMAN_MSG_A_FMT("Unhandled Atomic size: {}", IROp->Size);
-    }
-  }
-  else {
-    // TMP2-TMP3
-    switch (IROp->Size) {
-      case 1: {
-        aarch64::Label LoopTop;
-        bind(&LoopTop);
-        ldaxrb(TMP2.W(), MemOperand(MemSrc));
-        stlxrb(TMP4.W(), GetReg<RA_32>(Op->Value.ID()), MemOperand(MemSrc));
-        cbnz(TMP4.W(), &LoopTop);
-        uxtb(GetReg<RA_32>(Node), TMP2.W());
-        break;
-      }
-      case 2: {
-        aarch64::Label LoopTop;
-        bind(&LoopTop);
-        ldaxrh(TMP2.W(), MemOperand(MemSrc));
-        stlxrh(TMP4.W(), GetReg<RA_32>(Op->Value.ID()), MemOperand(MemSrc));
-        cbnz(TMP4.W(), &LoopTop);
-        uxtw(GetReg<RA_32>(Node), TMP2.W());
-        break;
-      }
-      case 4: {
-        aarch64::Label LoopTop;
-        bind(&LoopTop);
-        ldaxr(TMP2.W(), MemOperand(MemSrc));
-        stlxr(TMP4.W(), GetReg<RA_32>(Op->Value.ID()), MemOperand(MemSrc));
-        cbnz(TMP4.W(), &LoopTop);
-        mov(GetReg<RA_32>(Node), TMP2.W());
-        break;
-      }
-      case 8: {
-        aarch64::Label LoopTop;
-        bind(&LoopTop);
-        ldaxr(TMP2, MemOperand(MemSrc));
-        stlxr(TMP4, GetReg<RA_64>(Op->Value.ID()), MemOperand(MemSrc));
-        cbnz(TMP4, &LoopTop);
-        mov(GetReg<RA_64>(Node), TMP2.X());
-        break;
-      }
-      default:  LOGMAN_MSG_A_FMT("Unhandled Atomic size: {}", IROp->Size);
-    }
-  }
-}
-
-DEF_OP(AtomicFetchAdd) {
-  auto Op = IROp->C<IR::IROp_AtomicFetchAdd>();
-  auto MemSrc = GetReg<RA_64>(Op->Addr.ID());
-
-  if (CTX->HostFeatures.SupportsAtomics) {
-    switch (IROp->Size) {
-    case 1: ldaddalb(GetReg<RA_32>(Op->Value.ID()), GetReg<RA_32>(Node), MemOperand(MemSrc)); break;
-    case 2: ldaddalh(GetReg<RA_32>(Op->Value.ID()), GetReg<RA_32>(Node), MemOperand(MemSrc)); break;
-    case 4: ldaddal(GetReg<RA_32>(Op->Value.ID()), GetReg<RA_32>(Node), MemOperand(MemSrc)); break;
-    case 8: ldaddal(GetReg<RA_64>(Op->Value.ID()), GetReg<RA_64>(Node), MemOperand(MemSrc)); break;
-    default:  LOGMAN_MSG_A_FMT("Unhandled Atomic size: {}", IROp->Size);
-    }
-  }
-  else {
-    // TMP2-TMP3
-    switch (IROp->Size) {
-      case 1: {
-        aarch64::Label LoopTop;
-        bind(&LoopTop);
-        ldaxrb(TMP2.W(), MemOperand(MemSrc));
-        add(TMP3.W(), TMP2.W(), GetReg<RA_32>(Op->Value.ID()));
-        stlxrb(TMP4.W(), TMP3.W(), MemOperand(MemSrc));
-        cbnz(TMP4.W(), &LoopTop);
-        mov(GetReg<RA_32>(Node), TMP2.W());
-        break;
-      }
-      case 2: {
-        aarch64::Label LoopTop;
-        bind(&LoopTop);
-        ldaxrh(TMP2.W(), MemOperand(MemSrc));
-        add(TMP3.W(), TMP2.W(), GetReg<RA_32>(Op->Value.ID()));
-        stlxrh(TMP4.W(), TMP3.W(), MemOperand(MemSrc));
-        cbnz(TMP4.W(), &LoopTop);
-        mov(GetReg<RA_32>(Node), TMP2.W());
-        break;
-      }
-      case 4: {
-        aarch64::Label LoopTop;
-        bind(&LoopTop);
-        ldaxr(TMP2.W(), MemOperand(MemSrc));
-        add(TMP3.W(), TMP2.W(), GetReg<RA_32>(Op->Value.ID()));
-        stlxr(TMP4.W(), TMP3.W(), MemOperand(MemSrc));
-        cbnz(TMP4.W(), &LoopTop);
-        mov(GetReg<RA_32>(Node), TMP2.W());
-        break;
-      }
-      case 8: {
-        aarch64::Label LoopTop;
-        bind(&LoopTop);
-        ldaxr(TMP2, MemOperand(MemSrc));
-        add(TMP3, TMP2, GetReg<RA_64>(Op->Value.ID()));
-        stlxr(TMP4, TMP3, MemOperand(MemSrc));
-        cbnz(TMP4, &LoopTop);
-        mov(GetReg<RA_64>(Node), TMP2);
-        break;
-      }
-      default:  LOGMAN_MSG_A_FMT("Unhandled Atomic size: {}", IROp->Size);
-    }
-  }
-}
-
-DEF_OP(AtomicFetchSub) {
-  auto Op = IROp->C<IR::IROp_AtomicFetchSub>();
-  auto MemSrc = GetReg<RA_64>(Op->Addr.ID());
-
-  if (CTX->HostFeatures.SupportsAtomics) {
-    neg(TMP2, GetReg<RA_64>(Op->Value.ID()));
-    switch (IROp->Size) {
-    case 1: ldaddalb(TMP2.W(), GetReg<RA_32>(Node), MemOperand(MemSrc)); break;
-    case 2: ldaddalh(TMP2.W(), GetReg<RA_32>(Node), MemOperand(MemSrc)); break;
-    case 4: ldaddal(TMP2.W(), GetReg<RA_32>(Node), MemOperand(MemSrc)); break;
-    case 8: ldaddal(TMP2.X(), GetReg<RA_64>(Node), MemOperand(MemSrc)); break;
-    default:  LOGMAN_MSG_A_FMT("Unhandled Atomic size: {}", IROp->Size);
-    }
-  }
-  else {
-    // TMP2-TMP3
-    switch (IROp->Size) {
-      case 1: {
-        aarch64::Label LoopTop;
-        bind(&LoopTop);
-        ldaxrb(TMP2.W(), MemOperand(MemSrc));
-        sub(TMP3.W(), TMP2.W(), GetReg<RA_32>(Op->Value.ID()));
-        stlxrb(TMP4.W(), TMP3.W(), MemOperand(MemSrc));
-        cbnz(TMP4.W(), &LoopTop);
-        mov(GetReg<RA_32>(Node), TMP2.W());
-        break;
-      }
-      case 2: {
-        aarch64::Label LoopTop;
-        bind(&LoopTop);
-        ldaxrh(TMP2.W(), MemOperand(MemSrc));
-        sub(TMP3.W(), TMP2.W(), GetReg<RA_32>(Op->Value.ID()));
-        stlxrh(TMP4.W(), TMP3.W(), MemOperand(MemSrc));
-        cbnz(TMP4.W(), &LoopTop);
-        mov(GetReg<RA_32>(Node), TMP2.W());
-        break;
-      }
-      case 4: {
-        aarch64::Label LoopTop;
-        bind(&LoopTop);
-        ldaxr(TMP2.W(), MemOperand(MemSrc));
-        sub(TMP3.W(), TMP2.W(), GetReg<RA_32>(Op->Value.ID()));
-        stlxr(TMP4.W(), TMP3.W(), MemOperand(MemSrc));
-        cbnz(TMP4.W(), &LoopTop);
-        mov(GetReg<RA_32>(Node), TMP2.W());
-        break;
-      }
-      case 8: {
-        aarch64::Label LoopTop;
-        bind(&LoopTop);
-        ldaxr(TMP2, MemOperand(MemSrc));
-        sub(TMP3, TMP2, GetReg<RA_64>(Op->Value.ID()));
-        stlxr(TMP4, TMP3, MemOperand(MemSrc));
-        cbnz(TMP4, &LoopTop);
-        mov(GetReg<RA_64>(Node), TMP2);
-        break;
-      }
-      default:  LOGMAN_MSG_A_FMT("Unhandled Atomic size: {}", IROp->Size);
-    }
-  }
-}
-
-DEF_OP(AtomicFetchAnd) {
-  auto Op = IROp->C<IR::IROp_AtomicFetchAnd>();
-  auto MemSrc = GetReg<RA_64>(Op->Addr.ID());
-
-  if (CTX->HostFeatures.SupportsAtomics) {
-    mvn(TMP2, GetReg<RA_64>(Op->Value.ID()));
-    switch (IROp->Size) {
-    case 1: ldclralb(TMP2.W(), GetReg<RA_32>(Node), MemOperand(MemSrc)); break;
-    case 2: ldclralh(TMP2.W(), GetReg<RA_32>(Node), MemOperand(MemSrc)); break;
-    case 4: ldclral(TMP2.W(), GetReg<RA_32>(Node), MemOperand(MemSrc)); break;
-    case 8: ldclral(TMP2.X(), GetReg<RA_64>(Node), MemOperand(MemSrc)); break;
-    default:  LOGMAN_MSG_A_FMT("Unhandled Atomic size: {}", IROp->Size);
-    }
-  }
-  else {
-    // TMP2-TMP3
-    switch (IROp->Size) {
-      case 1: {
-        aarch64::Label LoopTop;
-        bind(&LoopTop);
-        ldaxrb(TMP2.W(), MemOperand(MemSrc));
-        and_(TMP3.W(), TMP2.W(), GetReg<RA_32>(Op->Value.ID()));
-        stlxrb(TMP4.W(), TMP3.W(), MemOperand(MemSrc));
-        cbnz(TMP4.W(), &LoopTop);
-        mov(GetReg<RA_32>(Node), TMP2.W());
-        break;
-      }
-      case 2: {
-        aarch64::Label LoopTop;
-        bind(&LoopTop);
-        ldaxrh(TMP2.W(), MemOperand(MemSrc));
-        and_(TMP3.W(), TMP2.W(), GetReg<RA_32>(Op->Value.ID()));
-        stlxrh(TMP4.W(), TMP3.W(), MemOperand(MemSrc));
-        cbnz(TMP4.W(), &LoopTop);
-        mov(GetReg<RA_32>(Node), TMP2.W());
-        break;
-      }
-      case 4: {
-        aarch64::Label LoopTop;
-        bind(&LoopTop);
-        ldaxr(TMP2.W(), MemOperand(MemSrc));
-        and_(TMP3.W(), TMP2.W(), GetReg<RA_32>(Op->Value.ID()));
-        stlxr(TMP4.W(), TMP3.W(), MemOperand(MemSrc));
-        cbnz(TMP4.W(), &LoopTop);
-        mov(GetReg<RA_32>(Node), TMP2.W());
-        break;
-      }
-      case 8: {
-        aarch64::Label LoopTop;
-        bind(&LoopTop);
-        ldaxr(TMP2, MemOperand(MemSrc));
-        and_(TMP3, TMP2, GetReg<RA_64>(Op->Value.ID()));
-        stlxr(TMP4, TMP3, MemOperand(MemSrc));
-        cbnz(TMP4, &LoopTop);
-        mov(GetReg<RA_64>(Node), TMP2);
-        break;
-      }
-      default:  LOGMAN_MSG_A_FMT("Unhandled Atomic size: {}", IROp->Size);
-    }
-  }
-}
-
-DEF_OP(AtomicFetchOr) {
-  auto Op = IROp->C<IR::IROp_AtomicFetchOr>();
-  auto MemSrc = GetReg<RA_64>(Op->Addr.ID());
-
-  if (CTX->HostFeatures.SupportsAtomics) {
-    switch (IROp->Size) {
-    case 1: ldsetalb(GetReg<RA_32>(Op->Value.ID()), GetReg<RA_32>(Node), MemOperand(MemSrc)); break;
-    case 2: ldsetalh(GetReg<RA_32>(Op->Value.ID()), GetReg<RA_32>(Node), MemOperand(MemSrc)); break;
-    case 4: ldsetal(GetReg<RA_32>(Op->Value.ID()), GetReg<RA_32>(Node), MemOperand(MemSrc)); break;
-    case 8: ldsetal(GetReg<RA_64>(Op->Value.ID()), GetReg<RA_64>(Node), MemOperand(MemSrc)); break;
-    default:  LOGMAN_MSG_A_FMT("Unhandled Atomic size: {}", IROp->Size);
-    }
-  }
-  else {
-    // TMP2-TMP3
-    switch (IROp->Size) {
-      case 1: {
-        aarch64::Label LoopTop;
-        bind(&LoopTop);
-        ldaxrb(TMP2.W(), MemOperand(MemSrc));
-        orr(TMP3.W(), TMP2.W(), GetReg<RA_32>(Op->Value.ID()));
-        stlxrb(TMP4.W(), TMP3.W(), MemOperand(MemSrc));
-        cbnz(TMP4.W(), &LoopTop);
-        mov(GetReg<RA_32>(Node), TMP2.W());
-        break;
-      }
-      case 2: {
-        aarch64::Label LoopTop;
-        bind(&LoopTop);
-        ldaxrh(TMP2.W(), MemOperand(MemSrc));
-        orr(TMP3.W(), TMP2.W(), GetReg<RA_32>(Op->Value.ID()));
-        stlxrh(TMP4.W(), TMP3.W(), MemOperand(MemSrc));
-        cbnz(TMP4.W(), &LoopTop);
-        mov(GetReg<RA_32>(Node), TMP2.W());
-        break;
-      }
-      case 4: {
-        aarch64::Label LoopTop;
-        bind(&LoopTop);
-        ldaxr(TMP2.W(), MemOperand(MemSrc));
-        orr(TMP3.W(), TMP2.W(), GetReg<RA_32>(Op->Value.ID()));
-        stlxr(TMP4.W(), TMP3.W(), MemOperand(MemSrc));
-        cbnz(TMP4.W(), &LoopTop);
-        mov(GetReg<RA_32>(Node), TMP2.W());
-        break;
-      }
-      case 8: {
-        aarch64::Label LoopTop;
-        bind(&LoopTop);
-        ldaxr(TMP2, MemOperand(MemSrc));
-        orr(TMP3, TMP2, GetReg<RA_64>(Op->Value.ID()));
-        stlxr(TMP4, TMP3, MemOperand(MemSrc));
-        cbnz(TMP4, &LoopTop);
-        mov(GetReg<RA_64>(Node), TMP2);
-        break;
-      }
-      default:  LOGMAN_MSG_A_FMT("Unhandled Atomic size: {}", IROp->Size);
-    }
-  }
-}
-
-DEF_OP(AtomicFetchXor) {
-  auto Op = IROp->C<IR::IROp_AtomicFetchXor>();
-  auto MemSrc = GetReg<RA_64>(Op->Addr.ID());
-
-  if (CTX->HostFeatures.SupportsAtomics) {
-    switch (IROp->Size) {
-    case 1: ldeoralb(GetReg<RA_32>(Op->Value.ID()), GetReg<RA_32>(Node), MemOperand(MemSrc)); break;
-    case 2: ldeoralh(GetReg<RA_32>(Op->Value.ID()), GetReg<RA_32>(Node), MemOperand(MemSrc)); break;
-    case 4: ldeoral(GetReg<RA_32>(Op->Value.ID()), GetReg<RA_32>(Node), MemOperand(MemSrc)); break;
-    case 8: ldeoral(GetReg<RA_64>(Op->Value.ID()), GetReg<RA_64>(Node), MemOperand(MemSrc)); break;
-    default:  LOGMAN_MSG_A_FMT("Unhandled Atomic size: {}", IROp->Size);
-    }
-  }
-  else {
-    // TMP2-TMP3
-    switch (IROp->Size) {
-      case 1: {
-        aarch64::Label LoopTop;
-        bind(&LoopTop);
-        ldaxrb(TMP2.W(), MemOperand(MemSrc));
-        eor(TMP3.W(), TMP2.W(), GetReg<RA_32>(Op->Value.ID()));
-        stlxrb(TMP4.W(), TMP3.W(), MemOperand(MemSrc));
-        cbnz(TMP4.W(), &LoopTop);
-        mov(GetReg<RA_32>(Node), TMP2.W());
-        break;
-      }
-      case 2: {
-        aarch64::Label LoopTop;
-        bind(&LoopTop);
-        ldaxrh(TMP2.W(), MemOperand(MemSrc));
-        eor(TMP3.W(), TMP2.W(), GetReg<RA_32>(Op->Value.ID()));
-        stlxrh(TMP4.W(), TMP3.W(), MemOperand(MemSrc));
-        cbnz(TMP4.W(), &LoopTop);
-        mov(GetReg<RA_32>(Node), TMP2.W());
-        break;
-      }
-      case 4: {
-        aarch64::Label LoopTop;
-        bind(&LoopTop);
-        ldaxr(TMP2.W(), MemOperand(MemSrc));
-        eor(TMP3.W(), TMP2.W(), GetReg<RA_32>(Op->Value.ID()));
-        stlxr(TMP4.W(), TMP3.W(), MemOperand(MemSrc));
-        cbnz(TMP4.W(), &LoopTop);
-        mov(GetReg<RA_32>(Node), TMP2.W());
-        break;
-      }
-      case 8: {
-        aarch64::Label LoopTop;
-        bind(&LoopTop);
-        ldaxr(TMP2, MemOperand(MemSrc));
-        eor(TMP3, TMP2, GetReg<RA_64>(Op->Value.ID()));
-        stlxr(TMP4, TMP3, MemOperand(MemSrc));
-        cbnz(TMP4, &LoopTop);
-        mov(GetReg<RA_64>(Node), TMP2);
-        break;
-      }
-      default:  LOGMAN_MSG_A_FMT("Unhandled Atomic size: {}", IROp->Size);
-    }
-  }
-}
-
-DEF_OP(AtomicFetchNeg) {
-  auto Op = IROp->C<IR::IROp_AtomicFetchNeg>();
-  auto MemSrc = GetReg<RA_64>(Op->Addr.ID());
-
-  // TMP2-TMP3
-  switch (IROp->Size) {
-    case 1: {
-      aarch64::Label LoopTop;
-      bind(&LoopTop);
-      ldaxrb(TMP2.W(), MemOperand(MemSrc));
-      neg(TMP3.W(), TMP2.W());
-      stlxrb(TMP4.W(), TMP3.W(), MemOperand(MemSrc));
-      cbnz(TMP4.W(), &LoopTop);
-      mov(GetReg<RA_32>(Node), TMP2.W());
-      break;
-    }
-    case 2: {
-      aarch64::Label LoopTop;
-      bind(&LoopTop);
-      ldaxrh(TMP2.W(), MemOperand(MemSrc));
-      neg(TMP3.W(), TMP2.W());
-      stlxrh(TMP4.W(), TMP3.W(), MemOperand(MemSrc));
-      cbnz(TMP4.W(), &LoopTop);
-      mov(GetReg<RA_32>(Node), TMP2.W());
-      break;
-    }
-    case 4: {
-      aarch64::Label LoopTop;
-      bind(&LoopTop);
-      ldaxr(TMP2.W(), MemOperand(MemSrc));
-      neg(TMP3.W(), TMP2.W());
-      stlxr(TMP4.W(), TMP3.W(), MemOperand(MemSrc));
-      cbnz(TMP4.W(), &LoopTop);
-      mov(GetReg<RA_32>(Node), TMP2.W());
-      break;
-    }
-    case 8: {
-      aarch64::Label LoopTop;
-      bind(&LoopTop);
-      ldaxr(TMP2, MemOperand(MemSrc));
-      neg(TMP3, TMP2);
-      stlxr(TMP4, TMP3, MemOperand(MemSrc));
-      cbnz(TMP4, &LoopTop);
-      mov(GetReg<RA_64>(Node), TMP2);
-      break;
-    }
-    default:  LOGMAN_MSG_A_FMT("Unhandled Atomic size: {}", IROp->Size);
-  }
-}
-
-#undef DEF_OP
-void Arm64JITCore::RegisterAtomicHandlers() {
-#define REGISTER_OP(op, x) OpHandlers[FEXCore::IR::IROps::OP_##op] = &Arm64JITCore::Op_##x
-  REGISTER_OP(CASPAIR,        CASPair);
-  REGISTER_OP(CAS,            CAS);
-  REGISTER_OP(ATOMICADD,      AtomicAdd);
-  REGISTER_OP(ATOMICSUB,      AtomicSub);
-  REGISTER_OP(ATOMICAND,      AtomicAnd);
-  REGISTER_OP(ATOMICOR,       AtomicOr);
-  REGISTER_OP(ATOMICXOR,      AtomicXor);
-  REGISTER_OP(ATOMICSWAP,     AtomicSwap);
-  REGISTER_OP(ATOMICFETCHADD, AtomicFetchAdd);
-  REGISTER_OP(ATOMICFETCHSUB, AtomicFetchSub);
-  REGISTER_OP(ATOMICFETCHAND, AtomicFetchAnd);
-  REGISTER_OP(ATOMICFETCHOR,  AtomicFetchOr);
-  REGISTER_OP(ATOMICFETCHXOR, AtomicFetchXor);
-  REGISTER_OP(ATOMICFETCHNEG, AtomicFetchNeg);
-#undef REGISTER_OP
-}
-}
-
@@ -1,515 +0,0 @@
-/*
-$info$
-tags: backend|arm64
-$end_info$
-*/
-
-#include "Interface/Context/Context.h"
-#include "FEXCore/IR/IR.h"
-#include "Interface/Core/LookupCache.h"
-
-#include "Interface/Core/JIT/Arm64/JITClass.h"
-#include "Interface/Core/InternalThreadState.h"
-
-#include <FEXCore/Core/X86Enums.h>
-#include <FEXCore/HLE/SyscallHandler.h>
-#include <FEXCore/Utils/MathUtils.h>
-#include <Interface/HLE/Thunks/Thunks.h>
-
-namespace FEXCore::CPU {
-using namespace vixl;
-using namespace vixl::aarch64;
-#define DEF_OP(x) void Arm64JITCore::Op_##x(IR::IROp_Header *IROp, IR::NodeID Node)
-
-DEF_OP(SignalReturn) {
-  // First we must reset the stack
-  ResetStack();
-
-  // Now branch to our signal return helper
-  // This can't be a direct branch since the code needs to live at a constant location
-  ldr(x0, MemOperand(STATE, offsetof(FEXCore::Core::CpuStateFrame, Pointers.Common.SignalReturnHandler)));
-  br(x0);
-}
-
-DEF_OP(CallbackReturn) {
-
-  // spill back to CTX
-  SpillStaticRegs();
-
-  // First we must reset the stack
-  ResetStack();
-
-  // We can now lower the ref counter again
-
-  ldr(w2, MemOperand(STATE, offsetof(FEXCore::Core::CpuStateFrame, SignalHandlerRefCounter)));
-  sub(w2, w2, 1);
-  str(w2, MemOperand(STATE, offsetof(FEXCore::Core::CpuStateFrame, SignalHandlerRefCounter)));
-
-  // We need to adjust an additional 8 bytes to get back to the original "misaligned" RSP state
-  ldr(x2, MemOperand(STATE, offsetof(FEXCore::Core::CpuStateFrame, State.gregs[X86State::REG_RSP])));
-  add(x2, x2, 8);
-  str(x2, MemOperand(STATE, offsetof(FEXCore::Core::CpuStateFrame, State.gregs[X86State::REG_RSP])));
-
-  PopCalleeSavedRegisters();
-
-  // Return to the thunk
-  ret();
-}
-
-DEF_OP(ExitFunction) {
-  auto Op = IROp->C<IR::IROp_ExitFunction>();
-
-  Label FullLookup;
-
-  ResetStack();
-
-  aarch64::Register RipReg;
-  uint64_t NewRIP;
-
-  if (IsInlineConstant(Op->NewRIP, &NewRIP) || IsInlineEntrypointOffset(Op->NewRIP, &NewRIP)) {
-    Literal l_BranchHost{ThreadState->CurrentFrame->Pointers.Common.ExitFunctionLinker};
-    Literal l_BranchGuest{NewRIP};
-
-    ldr(x0, &l_BranchHost);
-    blr(x0);
-
-    place(&l_BranchHost);
-    place(&l_BranchGuest);
-  } else {
-    RipReg = GetReg<RA_64>(Op->NewRIP.ID());
-
-    // L1 Cache
-    ldr(x0, MemOperand(STATE, offsetof(FEXCore::Core::CpuStateFrame, Pointers.Common.L1Pointer)));
-
-    and_(x3, RipReg, LookupCache::L1_ENTRIES_MASK);
-    add(x0, x0, Operand(x3, Shift::LSL, 4));
-
-    ldp(x1, x0, MemOperand(x0));
-    cmp(x0, RipReg);
-    b(&FullLookup, Condition::ne);
-    br(x1);
-
-    bind(&FullLookup);
-    ldr(TMP1, MemOperand(STATE, offsetof(FEXCore::Core::CpuStateFrame, Pointers.Common.DispatcherLoopTop)));
-    str(RipReg, MemOperand(STATE, offsetof(FEXCore::Core::CpuStateFrame, State.rip)));
-    br(TMP1);
-  }
-}
-
-DEF_OP(Jump) {
-  const auto Op = IROp->C<IR::IROp_Jump>();
-  const auto Target = Op->TargetBlock.ID();
-
-  PendingTargetLabel = &JumpTargets.try_emplace(Target).first->second;
-}
-
-#define GRCMP(Node) (Op->CompareSize == 4 ? GetReg<RA_32>(Node) : GetReg<RA_64>(Node))
-#define GRFCMP(Node) (Op->CompareSize == 4 ? GetDst(Node).S() : GetDst(Node).D())
-
-static Condition MapBranchCC(IR::CondClassType Cond) {
-  switch (Cond.Val) {
-  case FEXCore::IR::COND_EQ: return Condition::eq;
-  case FEXCore::IR::COND_NEQ: return Condition::ne;
-  case FEXCore::IR::COND_SGE: return Condition::ge;
-  case FEXCore::IR::COND_SLT: return Condition::lt;
-  case FEXCore::IR::COND_SGT: return Condition::gt;
-  case FEXCore::IR::COND_SLE: return Condition::le;
-  case FEXCore::IR::COND_UGE: return Condition::cs;
-  case FEXCore::IR::COND_ULT: return Condition::cc;
-  case FEXCore::IR::COND_UGT: return Condition::hi;
-  case FEXCore::IR::COND_ULE: return Condition::ls;
-  case FEXCore::IR::COND_FLU: return Condition::lt;
-  case FEXCore::IR::COND_FGE: return Condition::ge;
-  case FEXCore::IR::COND_FLEU:return Condition::le;
-  case FEXCore::IR::COND_FGT: return Condition::gt;
-  case FEXCore::IR::COND_FU:  return Condition::vs;
-  case FEXCore::IR::COND_FNU: return Condition::vc;
-  case FEXCore::IR::COND_VS:
-  case FEXCore::IR::COND_VC:
-  case FEXCore::IR::COND_MI:
-  case FEXCore::IR::COND_PL:
-  default:
-  LOGMAN_MSG_A_FMT("Unsupported compare type");
-  return Condition::nv;
-  }
-}
-
-
-DEF_OP(CondJump) {
-  auto Op = IROp->C<IR::IROp_CondJump>();
-
-  Label *TrueTargetLabel = &JumpTargets.try_emplace(Op->TrueBlock.ID()).first->second;
-
-  uint64_t Const;
-  const bool isConst = IsInlineConstant(Op->Cmp2, &Const);
-
-  if (isConst && Const == 0 && Op->Cond.Val == FEXCore::IR::COND_EQ) {
-    LOGMAN_THROW_A_FMT(IsGPR(Op->Cmp1.ID()), "CondJump: Expected GPR");
-    cbz(GRCMP(Op->Cmp1.ID()), TrueTargetLabel);
-  } else if (isConst && Const == 0 && Op->Cond.Val == FEXCore::IR::COND_NEQ) {
-    LOGMAN_THROW_A_FMT(IsGPR(Op->Cmp1.ID()), "CondJump: Expected GPR");
-    cbnz(GRCMP(Op->Cmp1.ID()), TrueTargetLabel);
-  } else {
-    if (IsGPR(Op->Cmp1.ID())) {
-      if (isConst) {
-        cmp(GRCMP(Op->Cmp1.ID()), Const);
-      } else {
-        cmp(GRCMP(Op->Cmp1.ID()), GRCMP(Op->Cmp2.ID()));
-      }
-    } else if (IsFPR(Op->Cmp1.ID())) {
-      fcmp(GRFCMP(Op->Cmp1.ID()), GRFCMP(Op->Cmp2.ID()));
-    } else {
-      LOGMAN_MSG_A_FMT("CondJump: Expected GPR or FPR");
-    }
-
-    b(TrueTargetLabel, MapBranchCC(Op->Cond));
-  }
-
-  PendingTargetLabel = &JumpTargets.try_emplace(Op->FalseBlock.ID()).first->second;
-}
-
-DEF_OP(Syscall) {
-  auto Op = IROp->C<IR::IROp_Syscall>();
-  // Arguments are passed as follows:
-  // X0: SyscallHandler
-  // X1: ThreadState
-  // X2: Pointer to SyscallArguments
-
-  FEXCore::IR::SyscallFlags Flags = Op->Flags;
-  PushDynamicRegsAndLR();
-
-  if ((Flags & FEXCore::IR::SyscallFlags::NOSYNCSTATEONENTRY) != FEXCore::IR::SyscallFlags::NOSYNCSTATEONENTRY) {
-    SpillStaticRegs();
-  }
-  else {
-    // Need to spill all caller saved registers still
-    SpillStaticRegs(true, CALLER_GPR_MASK, CALLER_FPR_MASK);
-  }
-
-  uint64_t SPOffset = AlignUp(FEXCore::HLE::SyscallArguments::MAX_ARGS * 8, 16);
-  sub(sp, sp, SPOffset);
-  for (uint32_t i = 0; i < FEXCore::HLE::SyscallArguments::MAX_ARGS; ++i) {
-    if (Op->Header.Args[i].IsInvalid()) continue;
-    str(GetReg<RA_64>(Op->Header.Args[i].ID()), MemOperand(sp, i * 8));
-  }
-
-  ldr(x0, MemOperand(STATE, offsetof(FEXCore::Core::CpuStateFrame, Pointers.Common.SyscallHandlerObj)));
-  ldr(x3, MemOperand(STATE, offsetof(FEXCore::Core::CpuStateFrame, Pointers.Common.SyscallHandlerFunc)));
-  mov(x1, STATE);
-  mov(x2, sp);
-#ifdef VIXL_SIMULATOR
-  GenerateIndirectRuntimeCall<uint64_t, void*, void*, void*>(x3);
-#else
-  blr(x3);
-#endif
-
-  add(sp, sp, SPOffset);
-
-  if ((Flags & FEXCore::IR::SyscallFlags::NOSYNCSTATEONENTRY) != FEXCore::IR::SyscallFlags::NOSYNCSTATEONENTRY &&
-      (Flags & FEXCore::IR::SyscallFlags::NORETURN) != FEXCore::IR::SyscallFlags::NORETURN) {
-    FillStaticRegs();
-  }
-  else {
-    // Result is now in x0
-    // Fix the stack and any values that were stepped on
-    FillStaticRegs(true, CALLER_GPR_MASK, CALLER_FPR_MASK);
-  }
-
-  PopDynamicRegsAndLR();
-
-  if ((Flags & FEXCore::IR::SyscallFlags::NORETURN) != FEXCore::IR::SyscallFlags::NORETURN) {
-    // Move result to its destination register
-    mov(GetReg<RA_64>(Node), x0);
-  }
-}
-
-DEF_OP(InlineSyscall) {
-  auto Op = IROp->C<IR::IROp_InlineSyscall>();
-  // Arguments are passed as follows:
-  // X8: SyscallNumber - RA INTERSECT
-  // X0: Arg0 & Return
-  // X1: Arg1
-  // X2: Arg2
-  // X3: Arg3
-  // X4: Arg4 - RA INTERSECT
-  // X5: Arg5 - RA INTERSECT
-  // X6: Arg6 - Doesn't exist in x86-64 land. RA INTERSECT
-
-  // One argument is removed from the SyscallArguments::MAX_ARGS since the first argument was syscall number
-  const static std::array<vixl::aarch64::Register, FEXCore::HLE::SyscallArguments::MAX_ARGS-1> RegArgs = {{
-    x0, x1, x2, x3, x4, x5
-  }};
-
-  bool Intersects{};
-  // We always need to spill x8 since we can't know if it is live at this SSA location
-  uint32_t SpillMask = 1U << 8;
-  for (uint32_t i = 0; i < FEXCore::HLE::SyscallArguments::MAX_ARGS-1; ++i) {
-    if (Op->Header.Args[i].IsInvalid()) break;
-
-    auto Reg = GetReg<RA_64>(Op->Header.Args[i].ID());
-    if (Reg.GetCode() == x8.GetCode() ||
-        Reg.GetCode() == x4.GetCode() ||
-        Reg.GetCode() == x5.GetCode()) {
-
-      SpillMask |= (1U << Reg.GetCode());
-      Intersects = true;
-    }
-  }
-  // XXX: For some reason spilling only the x4, x5, and x8 registers was causing issues
-  // Come back to this once investigation reveals why it fails the gvisor ioctl test
-  // For now override to all GPRs
-  SpillMask = ~0U;
-
-  // Ordering is incredibly important here
-  // We must spill any overlapping registers first THEN claim we are in a syscall without invalidating state at all
-  // Only spill the registers that intersect with our usage
-  SpillStaticRegs(false, SpillMask);
-
-  // Now that we are spilled, store in the state that we are in a syscall
-  // Still without overwriting registers that matter
-  // 16bit LoadConstant to be a single instruction
-  // We must always spill at least one register (x8) so this value always has a bit set
-  // This gives the signal handler a value to check to see if we are in a syscall at all
-  LoadConstant(x0, SpillMask & 0xFFFF);
-  str(x0, MemOperand(STATE, offsetof(FEXCore::Core::CpuStateFrame, InSyscallInfo)));
-
-  // Now that we have claimed to be a syscall we can set up the arguments
-  if (Intersects) {
-    for (uint32_t i = 0; i < FEXCore::HLE::SyscallArguments::MAX_ARGS-1; ++i) {
-      if (Op->Header.Args[i].IsInvalid()) break;
-
-      if (CTX->Config.Is64BitMode()) {
-        auto Reg = GetReg<RA_64>(Op->Header.Args[i].ID());
-        // In the case of intersection with x4, x5, or x8 then these are currently SRA
-        // for registers RAX, RBX, and RSI. Which have just been spilled
-        // Just load back from the context. Could be slightly smarter but this is fairly uncommon
-        if (Reg.GetCode() == x8.GetCode()) {
-          ldr(RegArgs[i], MemOperand(STATE, offsetof(FEXCore::Core::CpuStateFrame, State.gregs[X86State::REG_RSI])));
-        }
-        else if (Reg.GetCode() == x4.GetCode()) {
-          ldr(RegArgs[i], MemOperand(STATE, offsetof(FEXCore::Core::CpuStateFrame, State.gregs[X86State::REG_RAX])));
-        }
-        else if (Reg.GetCode() == x5.GetCode()) {
-          ldr(RegArgs[i], MemOperand(STATE, offsetof(FEXCore::Core::CpuStateFrame, State.gregs[X86State::REG_RBX])));
-        }
-      }
-    }
-
-    for (uint32_t i = 0; i < FEXCore::HLE::SyscallArguments::MAX_ARGS-1; ++i) {
-      if (Op->Header.Args[i].IsInvalid()) break;
-
-      if (CTX->Config.Is64BitMode()) {
-        auto Reg = GetReg<RA_64>(Op->Header.Args[i].ID());
-        // In the case of intersection with x4, x5, or x8 then these are currently SRA
-        // for registers RAX, RBX, and RSI. Which have just been spilled
-        // Just load back from the context. Could be slightly smarter but this is fairly uncommon
-        if (Reg.GetCode() == x8.GetCode()) {
-          ldr(RegArgs[i], MemOperand(STATE, offsetof(FEXCore::Core::CpuStateFrame, State.gregs[X86State::REG_RSI])));
-        }
-        else if (Reg.GetCode() == x4.GetCode()) {
-          ldr(RegArgs[i], MemOperand(STATE, offsetof(FEXCore::Core::CpuStateFrame, State.gregs[X86State::REG_RAX])));
-        }
-        else if (Reg.GetCode() == x5.GetCode()) {
-          ldr(RegArgs[i], MemOperand(STATE, offsetof(FEXCore::Core::CpuStateFrame, State.gregs[X86State::REG_RBX])));
-        }
-        else {
-          mov(RegArgs[i], Reg);
-        }
-      }
-      else {
-        auto Reg = GetReg<RA_32>(Op->Header.Args[i].ID());
-        if (Reg.GetCode() == w8.GetCode()) {
-          ldr(RegArgs[i].W(), MemOperand(STATE, offsetof(FEXCore::Core::CpuStateFrame, State.gregs[X86State::REG_RSI])));
-        }
-        else if (Reg.GetCode() == w4.GetCode()) {
-          ldr(RegArgs[i].W(), MemOperand(STATE, offsetof(FEXCore::Core::CpuStateFrame, State.gregs[X86State::REG_RAX])));
-        }
-        else if (Reg.GetCode() == w5.GetCode()) {
-          ldr(RegArgs[i].W(), MemOperand(STATE, offsetof(FEXCore::Core::CpuStateFrame, State.gregs[X86State::REG_RBX])));
-        }
-        else {
-          uxtw(RegArgs[i].W(), Reg);
-        }
-      }
-    }
-  }
-  else {
-    for (uint32_t i = 0; i < FEXCore::HLE::SyscallArguments::MAX_ARGS-1; ++i) {
-      if (Op->Header.Args[i].IsInvalid()) break;
-
-      if (CTX->Config.Is64BitMode()) {
-        mov(RegArgs[i], GetReg<RA_64>(Op->Header.Args[i].ID()));
-      }
-      else {
-        uxtw(RegArgs[i], GetReg<RA_64>(Op->Header.Args[i].ID()));
-      }
-    }
-  }
-
-  LoadConstant(x8, Op->HostSyscallNumber);
-  svc(0);
-  // On updated signal mask we can receive a signal RIGHT HERE
-
-  if ((Op->Flags & FEXCore::IR::SyscallFlags::NORETURN) != FEXCore::IR::SyscallFlags::NORETURN) {
-    // Now that we are done in the syscall we need to carefully peel back the state
-    // First unspill the registers from before
-    FillStaticRegs(false, SpillMask);
-
-    // Now the registers we've spilled are back in their original host registers
-    // We can safely claim we are no longer in a syscall
-    str(xzr, MemOperand(STATE, offsetof(FEXCore::Core::CpuStateFrame, InSyscallInfo)));
-
-    // Result is now in x0
-    // Move result to its destination register
-    if (CTX->Config.Is64BitMode()) {
-      mov(GetReg<RA_64>(Node), x0);
-    }
-    else {
-      uxtw(GetReg<RA_64>(Node), x0);
-    }
-  }
-}
-
-DEF_OP(Thunk) {
-  auto Op = IROp->C<IR::IROp_Thunk>();
-  // Arguments are passed as follows:
-  // X0: CTX
-  // X1: Args (from guest stack)
-
-  SpillStaticRegs(); // spill to ctx before ra64 spill
-
-  PushDynamicRegsAndLR();
-
-  mov(x0, GetReg<RA_64>(Op->ArgPtr.ID()));
-
-  auto thunkFn = ThreadState->CTX->ThunkHandler->LookupThunk(Op->ThunkNameHash);
-  LoadConstant(x2, (uintptr_t)thunkFn);
-#ifdef VIXL_SIMULATOR
-  GenerateIndirectRuntimeCall<void, void*, void*>(x2);
-#else
-  blr(x2);
-#endif
-
-  PopDynamicRegsAndLR();
-
-  FillStaticRegs(); // load from ctx after ra64 refill
-}
-
-DEF_OP(ValidateCode) {
-  auto Op = IROp->C<IR::IROp_ValidateCode>();
-  const auto *OldCode = (const uint8_t *)&Op->CodeOriginalLow;
-  int len = Op->CodeLength;
-  int idx = 0;
-
-  LoadConstant(GetReg<RA_64>(Node), 0);
-  LoadConstant(x0, Entry + Op->Offset);
-  LoadConstant(x1, 1);
-
-  while (len >= 8)
-  {
-    ldr(x2, MemOperand(x0, idx));
-    LoadConstant(x3, *(const uint32_t *)(OldCode + idx));
-    cmp(x2, x3);
-    csel(GetReg<RA_64>(Node), GetReg<RA_64>(Node), x1, Condition::eq);
-    len -= 8;
-    idx += 8;
-  }
-  while (len >= 4)
-  {
-    ldr(w2, MemOperand(x0, idx));
-    LoadConstant(w3, *(const uint32_t *)(OldCode + idx));
-    cmp(w2, w3);
-    csel(GetReg<RA_64>(Node), GetReg<RA_64>(Node), x1, Condition::eq);
-    len -= 4;
-    idx += 4;
-  }
-  while (len >= 2)
-  {
-    ldrh(w2, MemOperand(x0, idx));
-    LoadConstant(w3, *(const uint16_t *)(OldCode + idx));
-    cmp(w2, w3);
-    csel(GetReg<RA_64>(Node), GetReg<RA_64>(Node), x1, Condition::eq);
-    len -= 2;
-    idx += 2;
-  }
-  while (len >= 1)
-  {
-    ldrb(w2, MemOperand(x0, idx));
-    LoadConstant(w3, *(const uint8_t *)(OldCode + idx));
-    cmp(w2, w3);
-    csel(GetReg<RA_64>(Node), GetReg<RA_64>(Node), x1, Condition::eq);
-    len -= 1;
-    idx += 1;
-  }
-}
-
-DEF_OP(ThreadRemoveCodeEntry) {
-  // Arguments are passed as follows:
-  // X0: Thread
-  // X1: RIP
-
-  PushDynamicRegsAndLR();
-
-  mov(x0, STATE);
-  LoadConstant(x1, Entry);
-
-  ldr(x2, MemOperand(STATE, offsetof(FEXCore::Core::CpuStateFrame, Pointers.Common.ThreadRemoveCodeEntryFromJIT)));
-  SpillStaticRegs();
-#ifdef VIXL_SIMULATOR
-  GenerateIndirectRuntimeCall<void, void*, void*>(x2);
-#else
-  blr(x2);
-#endif
-  FillStaticRegs();
-
-  // Fix the stack and any values that were stepped on
-  PopDynamicRegsAndLR();
-}
-
-DEF_OP(CPUID) {
-  auto Op = IROp->C<IR::IROp_CPUID>();
-
-  PushDynamicRegsAndLR();
-  SpillStaticRegs();
-
-  // x0 = CPUID Handler
-  // x1 = CPUID Function
-  // x2 = CPUID Leaf
-  ldr(x0, MemOperand(STATE, offsetof(FEXCore::Core::CpuStateFrame, Pointers.Common.CPUIDObj)));
-  ldr(x3, MemOperand(STATE, offsetof(FEXCore::Core::CpuStateFrame, Pointers.Common.CPUIDFunction)));
-  mov(x1, GetReg<RA_64>(Op->Function.ID()));
-  mov(x2, GetReg<RA_64>(Op->Leaf.ID()));
-#ifdef VIXL_SIMULATOR
-  GenerateIndirectRuntimeCall<__uint128_t, void*, uint64_t, uint64_t>(x3);
-#else
-  blr(x3);
-#endif
-
-  FillStaticRegs();
-  PopDynamicRegsAndLR();
-
-  // Results are in x0, x1
-  // Results want to be in a i64v2 vector
-  auto Dst = GetSrcPair<RA_64>(Node);
-  mov(Dst.first,  x0);
-  mov(Dst.second, x1);
-}
-
-#undef DEF_OP
-void Arm64JITCore::RegisterBranchHandlers() {
-#define REGISTER_OP(op, x) OpHandlers[FEXCore::IR::IROps::OP_##op] = &Arm64JITCore::Op_##x
-  REGISTER_OP(SIGNALRETURN,      SignalReturn);
-  REGISTER_OP(CALLBACKRETURN,    CallbackReturn);
-  REGISTER_OP(EXITFUNCTION,      ExitFunction);
-  REGISTER_OP(JUMP,              Jump);
-  REGISTER_OP(CONDJUMP,          CondJump);
-  REGISTER_OP(SYSCALL,           Syscall);
-  REGISTER_OP(INLINESYSCALL,     InlineSyscall);
-  REGISTER_OP(THUNK,             Thunk);
-  REGISTER_OP(VALIDATECODE,      ValidateCode);
-  REGISTER_OP(THREADREMOVECODEENTRY,   ThreadRemoveCodeEntry);
-  REGISTER_OP(CPUID,             CPUID);
-#undef REGISTER_OP
-}
-}
-
@@ -1,586 +0,0 @@
-/*
-$info$
-tags: backend|arm64
-$end_info$
-*/
-
-#include "Interface/Core/JIT/Arm64/JITClass.h"
-
-namespace FEXCore::CPU {
-
-using namespace vixl;
-using namespace vixl::aarch64;
-#define DEF_OP(x) void Arm64JITCore::Op_##x(IR::IROp_Header *IROp, IR::NodeID Node)
-DEF_OP(VInsGPR) {
-  const auto Op = IROp->C<IR::IROp_VInsGPR>();
-  const auto OpSize = IROp->Size;
-
-  const auto DestIdx = Op->DestIdx;
-  const auto ElementSize = Op->Header.ElementSize;
-  const auto Is256Bit = OpSize == Core::CPUState::XMM_AVX_REG_SIZE;
-
-  const auto Dst = GetDst(Node);
-  const auto DestVector = GetSrc(Op->DestVector.ID());
-
-  if (HostSupportsSVE && Is256Bit) {
-    const auto ElementSizeBits = ElementSize * 8;
-    const auto Offset = ElementSizeBits * DestIdx;
-
-    const auto SSEBitSize = Core::CPUState::XMM_SSE_REG_SIZE * 8;
-    const auto InUpperLane = Offset >= SSEBitSize;
-
-    // This is going to be a little gross. Pls forgive me.
-    // Since SVE has the whole vector length agnostic programming
-    // thing going on, we can't exactly freely insert entries into
-    // arbitrary locations in the vector.
-    //
-    // SVE *does* have INSR, however this only shifts the entire
-    // vector to the left by an element size and inserts a value
-    // at the beginning of the vector. Not *quite* what we need.
-    // (though INSR *is* very useful for other things).
-    //
-    // The idea is (in the case of the upper lane), move the upper
-    // lane down, insert into it and recombine with the lower lane.
-    //
-    // In the case of the lower lane, insert and then recombine with
-    // the upper lane.
-
-    if (InUpperLane) {
-      // Move the upper lane down for the insertion.
-      const auto CompactPred = p0;
-      not_(CompactPred.VnB(), PRED_TMP_32B.Zeroing(), PRED_TMP_16B.VnB());
-      compact(VTMP1.Z().VnD(), CompactPred, DestVector.Z().VnD());
-    }
-
-    // Put data in place for destructive SPLICE below.
-    mov(Dst.Z().VnD(), DestVector.Z().VnD());
-
-    // Inserts the GPR value into the given V register.
-    // Also automatically adjusts the index in the case of using the
-    // moved upper lane.
-    const auto Insert = [&](const aarch64::VRegister& reg, int index) {
-      switch (ElementSize) {
-        case 1:
-          if (InUpperLane) {
-            index -= 16;
-          }
-          ins(reg.V16B(), index, GetReg<RA_32>(Op->Src.ID()));
-          break;
-        case 2:
-          if (InUpperLane) {
-            index -= 8;
-          }
-          ins(reg.V8H(), index, GetReg<RA_32>(Op->Src.ID()));
-          break;
-        case 4:
-          if (InUpperLane) {
-            index -= 4;
-          }
-          ins(reg.V4S(), index, GetReg<RA_32>(Op->Src.ID()));
-          break;
-        case 8:
-          if (InUpperLane) {
-            index -= 2;
-          }
-          ins(reg.V2D(), index, GetReg<RA_64>(Op->Src.ID()));
-          break;
-        default:
-          LOGMAN_MSG_A_FMT("Unknown Element Size: {}", ElementSize);
-          break;
-      }
-    };
-
-    if (InUpperLane) {
-      Insert(VTMP1, DestIdx);
-      splice(Dst.Z().VnD(), PRED_TMP_16B, Dst.Z().VnD(), VTMP1.Z().VnD());
-    } else {
-      Insert(Dst, DestIdx);
-      splice(Dst.Z().VnD(), PRED_TMP_16B, Dst.Z().VnD(), DestVector.Z().VnD());
-    }
-  } else {
-    mov(Dst, DestVector);
-
-    switch (ElementSize) {
-      case 1: {
-        ins(Dst.V16B(), DestIdx, GetReg<RA_32>(Op->Src.ID()));
-        break;
-      }
-      case 2: {
-        ins(Dst.V8H(), DestIdx, GetReg<RA_32>(Op->Src.ID()));
-        break;
-      }
-      case 4: {
-        ins(Dst.V4S(), DestIdx, GetReg<RA_32>(Op->Src.ID()));
-        break;
-      }
-      case 8: {
-        ins(Dst.V2D(), DestIdx, GetReg<RA_64>(Op->Src.ID()));
-        break;
-      }
-      default:
-        LOGMAN_MSG_A_FMT("Unknown Element Size: {}", ElementSize);
-        break;
-    }
-  }
-}
-
-DEF_OP(VCastFromGPR) {
-  auto Op = IROp->C<IR::IROp_VCastFromGPR>();
-  switch (Op->Header.ElementSize) {
-    case 1:
-      uxtb(TMP1.W(), GetReg<RA_32>(Op->Src.ID()));
-      fmov(GetDst(Node).S(), TMP1.W());
-      break;
-    case 2:
-      uxth(TMP1.W(), GetReg<RA_32>(Op->Src.ID()));
-      fmov(GetDst(Node).S(), TMP1.W());
-      break;
-    case 4:
-      fmov(GetDst(Node).S(), GetReg<RA_32>(Op->Src.ID()).W());
-      break;
-    case 8:
-      fmov(GetDst(Node).D(), GetReg<RA_64>(Op->Src.ID()).X());
-      break;
-    default: LOGMAN_MSG_A_FMT("Unknown castGPR element size: {}", Op->Header.ElementSize);
-  }
-}
-
-DEF_OP(Float_FromGPR_S) {
-  const auto Op = IROp->C<IR::IROp_Float_FromGPR_S>();
-
-  const uint16_t ElementSize = Op->Header.ElementSize;
-  const uint16_t Conv = (ElementSize << 8) | Op->SrcElementSize;
-
-  switch (Conv) {
-    case 0x0404: { // Float <- int32_t
-      scvtf(GetDst(Node).S(), GetReg<RA_32>(Op->Src.ID()));
-      break;
-    }
-    case 0x0408: { // Float <- int64_t
-      scvtf(GetDst(Node).S(), GetReg<RA_64>(Op->Src.ID()));
-      break;
-    }
-    case 0x0804: { // Double <- int32_t
-      scvtf(GetDst(Node).D(), GetReg<RA_32>(Op->Src.ID()));
-      break;
-    }
-    case 0x0808: { // Double <- int64_t
-      scvtf(GetDst(Node).D(), GetReg<RA_64>(Op->Src.ID()));
-      break;
-    }
-    default:
-      LOGMAN_MSG_A_FMT("Unhandled conversion mask: Mask=0x{:04x}, ElementSize={}, SrcElementSize={}",
-                       Conv, ElementSize, Op->SrcElementSize);
-      break;
-  }
-}
-
-DEF_OP(Float_FToF) {
-  auto Op = IROp->C<IR::IROp_Float_FToF>();
-  const uint16_t Conv = (Op->Header.ElementSize << 8) | Op->SrcElementSize;
-  switch (Conv) {
-    case 0x0804: { // Double <- Float
-      fcvt(GetDst(Node).D(), GetSrc(Op->Scalar.ID()).S());
-      break;
-    }
-    case 0x0408: { // Float <- Double
-      fcvt(GetDst(Node).S(), GetSrc(Op->Scalar.ID()).D());
-      break;
-    }
-    default: LOGMAN_MSG_A_FMT("Unknown FCVT sizes: 0x{:x}", Conv);
-  }
-}
-
-DEF_OP(Vector_SToF) {
-  const auto Op = IROp->C<IR::IROp_Vector_SToF>();
-  const auto OpSize = IROp->Size;
-
-  const auto ElementSize = Op->Header.ElementSize;
-  const auto Is256Bit = OpSize == Core::CPUState::XMM_AVX_REG_SIZE;
-
-  const auto Dst = GetDst(Node);
-  const auto Vector = GetSrc(Op->Vector.ID());
-
-  if (HostSupportsSVE && Is256Bit) {
-    const auto Mask = PRED_TMP_32B.Merging();
-
-    switch (ElementSize) {
-      case 2:
-        scvtf(Dst.Z().VnH(), Mask, Vector.Z().VnH());
-        break;
-      case 4:
-        scvtf(Dst.Z().VnS(), Mask, Vector.Z().VnS());
-        break;
-      case 8:
-        scvtf(Dst.Z().VnD(), Mask, Vector.Z().VnD());
-        break;
-      default:
-        LOGMAN_MSG_A_FMT("Unknown Vector_SToF element size: {}", ElementSize);
-        break;
-    }
-  } else {
-    switch (ElementSize) {
-      case 2:
-        scvtf(Dst.V8H(), Vector.V8H());
-        break;
-      case 4:
-        scvtf(Dst.V4S(), Vector.V4S());
-        break;
-      case 8:
-        scvtf(Dst.V2D(), Vector.V2D());
-        break;
-      default:
-        LOGMAN_MSG_A_FMT("Unknown Vector_SToF element size: {}", ElementSize);
-        break;
-    }
-  }
-}
-
-DEF_OP(Vector_FToZS) {
-  const auto Op = IROp->C<IR::IROp_Vector_FToZS>();
-  const auto OpSize = IROp->Size;
-
-  const auto ElementSize = Op->Header.ElementSize;
-  const auto Is256Bit = OpSize == Core::CPUState::XMM_AVX_REG_SIZE;
-
-  const auto Dst = GetDst(Node);
-  const auto Vector = GetSrc(Op->Vector.ID());
-
-  if (HostSupportsSVE && Is256Bit) {
-    const auto Mask = PRED_TMP_32B.Merging();
-
-    switch (ElementSize) {
-      case 2:
-        fcvtzs(Dst.Z().VnH(), Mask, Vector.Z().VnH());
-        break;
-      case 4:
-        fcvtzs(Dst.Z().VnS(), Mask, Vector.Z().VnS());
-        break;
-      case 8:
-        fcvtzs(Dst.Z().VnD(), Mask, Vector.Z().VnD());
-        break;
-      default:
-        LOGMAN_MSG_A_FMT("Unknown Vector_FToZS element size: {}", ElementSize);
-        break;
-    }
-  } else {
-    switch (ElementSize) {
-      case 2:
-        fcvtzs(Dst.V8H(), Vector.V8H());
-        break;
-      case 4:
-        fcvtzs(Dst.V4S(), Vector.V4S());
-        break;
-      case 8:
-        fcvtzs(Dst.V2D(), Vector.V2D());
-        break;
-      default:
-        LOGMAN_MSG_A_FMT("Unknown Vector_FToZS element size: {}", ElementSize);
-        break;
-    }
-  }
-}
-
-DEF_OP(Vector_FToS) {
-  const auto Op = IROp->C<IR::IROp_Vector_FToS>();
-  const auto OpSize = IROp->Size;
-
-  const auto ElementSize = Op->Header.ElementSize;
-  const auto Is256Bit = OpSize == Core::CPUState::XMM_AVX_REG_SIZE;
-
-  const auto Dst = GetDst(Node);
-  const auto Vector = GetSrc(Op->Vector.ID());
-
-  if (HostSupportsSVE && Is256Bit) {
-    const auto Mask = PRED_TMP_32B.Merging();
-
-    switch (ElementSize) {
-      case 2:
-        frinti(Dst.Z().VnH(), Mask, Vector.Z().VnH());
-        fcvtzs(Dst.Z().VnH(), Mask, Dst.Z().VnH());
-        break;
-      case 4:
-        frinti(Dst.Z().VnS(), Mask, Vector.Z().VnS());
-        fcvtzs(Dst.Z().VnS(), Mask, Dst.Z().VnS());
-        break;
-      case 8:
-        frinti(Dst.Z().VnD(), Mask, Vector.Z().VnD());
-        fcvtzs(Dst.Z().VnD(), Mask, Dst.Z().VnD());
-        break;
-      default:
-        LOGMAN_MSG_A_FMT("Unknown Vector_FToS element size: {}", ElementSize);
-        break;
-    }
-  } else {
-    switch (ElementSize) {
-      case 2:
-        frinti(Dst.V8H(), Vector.V8H());
-        fcvtzs(Dst.V8H(), Dst.V8H());
-        break;
-      case 4:
-        frinti(Dst.V4S(), Vector.V4S());
-        fcvtzs(Dst.V4S(), Dst.V4S());
-        break;
-      case 8:
-        frinti(Dst.V2D(), Vector.V2D());
-        fcvtzs(Dst.V2D(), Dst.V2D());
-        break;
-      default:
-        LOGMAN_MSG_A_FMT("Unknown Vector_FToS element size: {}", ElementSize);
-        break;
-    }
-  }
-}
-
-DEF_OP(Vector_FToF) {
-  const auto Op = IROp->C<IR::IROp_Vector_FToF>();
-  const auto OpSize = IROp->Size;
-
-  const auto ElementSize = Op->Header.ElementSize;
-  const auto Is256Bit = OpSize == Core::CPUState::XMM_AVX_REG_SIZE;
-  const auto Conv = (ElementSize << 8) | Op->SrcElementSize;
-
-  const auto Dst = GetDst(Node);
-  const auto Vector = GetSrc(Op->Vector.ID());
-
-  if (HostSupportsSVE && Is256Bit) {
-    // Curiously, FCVTLT and FCVTNT have no bottom variants,
-    // and also interesting is that FCVTLT will iterate the
-    // source vector by accessing each odd element and storing
-    // them consecutively in the destination.
-    //
-    // FCVTNT is somewhat like the opposite. It will read each
-    // consecutive element, but store each result into every odd
-    // element in the destination vector.
-    //
-    // We need to undo the behavior of FCVTNT with UZP2. In the case
-    // of FCVTLT, we instead need to set the vector up with ZIP1, so
-    // that the elements will be processed correctly.
-
-    const auto Mask = PRED_TMP_32B.Merging();
-
-    switch (Conv) {
-      case 0x0402: { // Float <- Half
-        zip1(Dst.Z().VnH(), Vector.Z().VnH(), Vector.Z().VnH());
-        fcvtlt(Dst.Z().VnS(), Mask, Dst.Z().VnH());
-        break;
-      }
-      case 0x0804: { // Double <- Float
-        zip1(Dst.Z().VnS(), Vector.Z().VnS(), Vector.Z().VnS());
-        fcvtlt(Dst.Z().VnD(), Mask, Dst.Z().VnS());
-        break;
-      }
-      case 0x0204: { // Half <- Float
-        fcvtnt(Dst.Z().VnH(), Mask, Vector.Z().VnS());
-        uzp2(Dst.Z().VnH(), Dst.Z().VnH(), Dst.Z().VnH());
-        break;
-      }
-      case 0x0408: { // Float <- Double
-        fcvtnt(Dst.Z().VnS(), Mask, Vector.Z().VnD());
-        uzp2(Dst.Z().VnS(), Dst.Z().VnS(), Dst.Z().VnS());
-        break;
-      }
-      default:
-        LOGMAN_MSG_A_FMT("Unknown Vector_FToF Type : 0x{:04x}", Conv);
-        break;
-    }
-  } else {
-    switch (Conv) {
-      case 0x0402: { // Float <- Half
-        fcvtl(Dst.V4S(), Vector.V4H());
-        break;
-      }
-      case 0x0804: { // Double <- Float
-        fcvtl(Dst.V2D(), Vector.V2S());
-        break;
-      }
-      case 0x0204: { // Half <- Float
-        fcvtn(Dst.V4H(), Vector.V4S());
-        break;
-      }
-      case 0x0408: { // Float <- Double
-        fcvtn(Dst.V2S(), Vector.V2D());
-        break;
-      }
-      default:
-        LOGMAN_MSG_A_FMT("Unknown Vector_FToF Type : 0x{:04x}", Conv);
-        break;
-    }
-  }
-}
-
-DEF_OP(Vector_FToI) {
-  const auto Op = IROp->C<IR::IROp_Vector_FToI>();
-  const auto OpSize = IROp->Size;
-
-  const auto ElementSize = Op->Header.ElementSize;
-  const auto Is256Bit = OpSize == Core::CPUState::XMM_AVX_REG_SIZE;
-
-  const auto Dst = GetDst(Node);
-  const auto Vector = GetSrc(Op->Vector.ID());
-
-  if (HostSupportsSVE && Is256Bit) {
-    const auto Mask = PRED_TMP_32B.Merging();
-    
-    switch (Op->Round) {
-      case FEXCore::IR::Round_Nearest.Val:
-        switch (ElementSize) {
-          case 2:
-            frintn(Dst.Z().VnH(), Mask, Vector.Z().VnH());
-            break;
-          case 4:
-            frintn(Dst.Z().VnS(), Mask, Vector.Z().VnS());
-            break;
-          case 8:
-            frintn(Dst.Z().VnD(), Mask, Vector.Z().VnD());
-            break;
-        }
-        break;
-
-      case FEXCore::IR::Round_Negative_Infinity.Val:
-        switch (ElementSize) {
-          case 2:
-            frintm(Dst.Z().VnH(), Mask, Vector.Z().VnH());
-            break;
-          case 4:
-            frintm(Dst.Z().VnS(), Mask, Vector.Z().VnS());
-            break;
-          case 8:
-            frintm(Dst.Z().VnD(), Mask, Vector.Z().VnD());
-            break;
-        }
-        break;
-
-      case FEXCore::IR::Round_Positive_Infinity.Val:
-        switch (ElementSize) {
-          case 2:
-            frintp(Dst.Z().VnH(), Mask, Vector.Z().VnH());
-            break;
-          case 4:
-            frintp(Dst.Z().VnS(), Mask, Vector.Z().VnS());
-            break;
-          case 8:
-            frintp(Dst.Z().VnD(), Mask, Vector.Z().VnD());
-            break;
-        }
-        break;
-
-      case FEXCore::IR::Round_Towards_Zero.Val:
-        switch (ElementSize) {
-          case 2:
-            frintz(Dst.Z().VnH(), Mask, Vector.Z().VnH());
-            break;
-          case 4:
-            frintz(Dst.Z().VnS(), Mask, Vector.Z().VnS());
-            break;
-          case 8:
-            frintz(Dst.Z().VnD(), Mask, Vector.Z().VnD());
-            break;
-        }
-        break;
-
-      case FEXCore::IR::Round_Host.Val:
-        switch (ElementSize) {
-          case 2:
-            frinti(Dst.Z().VnH(), Mask, Vector.Z().VnH());
-            break;
-          case 4:
-            frinti(Dst.Z().VnS(), Mask, Vector.Z().VnS());
-            break;
-          case 8:
-            frinti(Dst.Z().VnD(), Mask, Vector.Z().VnD());
-            break;
-        }
-        break;
-    }
-  } else {
-    switch (Op->Round) {
-      case FEXCore::IR::Round_Nearest.Val:
-        switch (ElementSize) {
-          case 2:
-            frintn(Dst.V8H(), Vector.V8H());
-            break;
-          case 4:
-            frintn(Dst.V4S(), Vector.V4S());
-            break;
-          case 8:
-            frintn(Dst.V2D(), Vector.V2D());
-            break;
-        }
-        break;
-
-      case FEXCore::IR::Round_Negative_Infinity.Val:
-        switch (ElementSize) {
-          case 2:
-            frintm(Dst.V8H(), Vector.V8H());
-            break;
-          case 4:
-            frintm(Dst.V4S(), Vector.V4S());
-            break;
-          case 8:
-            frintm(Dst.V2D(), Vector.V2D());
-            break;
-        }
-        break;
-
-      case FEXCore::IR::Round_Positive_Infinity.Val:
-        switch (ElementSize) {
-          case 2:
-            frintp(Dst.V8H(), Vector.V8H());
-            break;
-          case 4:
-            frintp(Dst.V4S(), Vector.V4S());
-            break;
-          case 8:
-            frintp(Dst.V2D(), Vector.V2D());
-            break;
-        }
-        break;
-
-      case FEXCore::IR::Round_Towards_Zero.Val:
-        switch (ElementSize) {
-          case 2:
-            frintz(Dst.V8H(), Vector.V8H());
-            break;
-          case 4:
-            frintz(Dst.V4S(), Vector.V4S());
-            break;
-          case 8:
-            frintz(Dst.V2D(), Vector.V2D());
-            break;
-        }
-        break;
-
-      case FEXCore::IR::Round_Host.Val:
-        switch (ElementSize) {
-          case 2:
-            frinti(Dst.V8H(), Vector.V8H());
-            break;
-          case 4:
-            frinti(Dst.V4S(), Vector.V4S());
-            break;
-          case 8:
-            frinti(Dst.V2D(), Vector.V2D());
-            break;
-        }
-        break;
-    }
-  }
-}
-
-#undef DEF_OP
-void Arm64JITCore::RegisterConversionHandlers() {
-#define REGISTER_OP(op, x) OpHandlers[FEXCore::IR::IROps::OP_##op] = &Arm64JITCore::Op_##x
-  REGISTER_OP(VINSGPR,         VInsGPR);
-  REGISTER_OP(VCASTFROMGPR,    VCastFromGPR);
-  REGISTER_OP(FLOAT_FROMGPR_S, Float_FromGPR_S);
-  REGISTER_OP(FLOAT_FTOF,      Float_FToF);
-  REGISTER_OP(VECTOR_STOF,     Vector_SToF);
-  REGISTER_OP(VECTOR_FTOZS,    Vector_FToZS);
-  REGISTER_OP(VECTOR_FTOS,     Vector_FToS);
-  REGISTER_OP(VECTOR_FTOF,     Vector_FToF);
-  REGISTER_OP(VECTOR_FTOI,     Vector_FToI);
-#undef REGISTER_OP
-}
-}
-
@@ -1,146 +0,0 @@
-/*
-$info$
-tags: backend|arm64
-$end_info$
-*/
-
-#include "Interface/Core/JIT/Arm64/JITClass.h"
-#include "Interface/IR/Passes/RegisterAllocationPass.h"
-
-namespace FEXCore::CPU {
-using namespace vixl;
-using namespace vixl::aarch64;
-#define DEF_OP(x) void Arm64JITCore::Op_##x(IR::IROp_Header *IROp, IR::NodeID Node)
-
-DEF_OP(AESImc) {
-  auto Op = IROp->C<IR::IROp_VAESImc>();
-  aesimc(GetDst(Node).V16B(), GetSrc(Op->Vector.ID()).V16B());
-}
-
-DEF_OP(AESEnc) {
-	auto Op = IROp->C<IR::IROp_VAESEnc>();
-  eor(VTMP2.V16B(), VTMP2.V16B(), VTMP2.V16B());
-  mov(VTMP1.V16B(), GetSrc(Op->State.ID()).V16B());
-  aese(VTMP1.V16B(), VTMP2.V16B());
-  aesmc(VTMP1.V16B(), VTMP1.V16B());
-  eor(GetDst(Node).V16B(), VTMP1.V16B(), GetSrc(Op->Key.ID()).V16B());
-}
-
-DEF_OP(AESEncLast) {
-	auto Op = IROp->C<IR::IROp_VAESEncLast>();
-  eor(VTMP2.V16B(), VTMP2.V16B(), VTMP2.V16B());
-  mov(VTMP1.V16B(), GetSrc(Op->State.ID()).V16B());
-  aese(VTMP1.V16B(), VTMP2.V16B());
-  eor(GetDst(Node).V16B(), VTMP1.V16B(), GetSrc(Op->Key.ID()).V16B());
-}
-
-DEF_OP(AESDec) {
-	auto Op = IROp->C<IR::IROp_VAESDec>();
-  eor(VTMP2.V16B(), VTMP2.V16B(), VTMP2.V16B());
-  mov(VTMP1.V16B(), GetSrc(Op->State.ID()).V16B());
-  aesd(VTMP1.V16B(), VTMP2.V16B());
-  aesimc(VTMP1.V16B(), VTMP1.V16B());
-  eor(GetDst(Node).V16B(), VTMP1.V16B(), GetSrc(Op->Key.ID()).V16B());
-}
-
-DEF_OP(AESDecLast) {
-	auto Op = IROp->C<IR::IROp_VAESDecLast>();
-  eor(VTMP2.V16B(), VTMP2.V16B(), VTMP2.V16B());
-  mov(VTMP1.V16B(), GetSrc(Op->State.ID()).V16B());
-  aesd(VTMP1.V16B(), VTMP2.V16B());
-  eor(GetDst(Node).V16B(), VTMP1.V16B(), GetSrc(Op->Key.ID()).V16B());
-}
-
-DEF_OP(AESKeyGenAssist) {
-	auto Op = IROp->C<IR::IROp_VAESKeyGenAssist>();
-
-  aarch64::Literal ConstantLiteral (0x0C030609'0306090CULL, 0x040B0E01'0B0E0104ULL);
-  aarch64::Label PastConstant;
-
-  // Do a "regular" AESE step
-  eor(VTMP2.V16B(), VTMP2.V16B(), VTMP2.V16B());
-  mov(VTMP1.V16B(), GetSrc(Op->Src.ID()).V16B());
-  aese(VTMP1.V16B(), VTMP2.V16B());
-
-  // Do a table shuffle to undo ShiftRows
-  ldr(VTMP3, &ConstantLiteral);
-
-  // Now EOR in the RCON
-  if (Op->RCON) {
-    tbl(VTMP1.V16B(), VTMP1.V16B(), VTMP3.V16B());
-
-    LoadConstant(TMP1.W(), Op->RCON);
-    ins(VTMP2.V4S(), 1, TMP1.W());
-    ins(VTMP2.V4S(), 3, TMP1.W());
-    eor(GetDst(Node).V16B(), VTMP1.V16B(), VTMP2.V16B());
-  }
-  else {
-    tbl(GetDst(Node).V16B(), VTMP1.V16B(), VTMP3.V16B());
-  }
-
-  b(&PastConstant);
-  place(&ConstantLiteral);
-  bind(&PastConstant);
-}
-
-DEF_OP(CRC32) {
-  auto Op = IROp->C<IR::IROp_CRC32>();
-  switch (Op->SrcSize) {
-    case 1:
-      crc32cb(GetReg<RA_32>(Node), GetReg<RA_32>(Op->Src1.ID()), GetReg<RA_32>(Op->Src2.ID()));
-      break;
-    case 2:
-      crc32ch(GetReg<RA_32>(Node), GetReg<RA_32>(Op->Src1.ID()), GetReg<RA_32>(Op->Src2.ID()));
-      break;
-    case 4:
-      crc32cw(GetReg<RA_32>(Node), GetReg<RA_32>(Op->Src1.ID()), GetReg<RA_32>(Op->Src2.ID()));
-      break;
-    case 8:
-      crc32cx(GetReg<RA_32>(Node), GetReg<RA_32>(Op->Src1.ID()), GetReg<RA_64>(Op->Src2.ID()));
-      break;
-    default: LOGMAN_MSG_A_FMT("Unknown CRC32 size: {}", Op->SrcSize);
-  }
-}
-
-DEF_OP(PCLMUL) {
-  auto Op = IROp->C<IR::IROp_PCLMUL>();
-
-  auto Dst  = GetDst(Node).Q();
-  auto Src1 = GetSrc(Op->Src1.ID()).V2D();
-  auto Src2 = GetSrc(Op->Src2.ID()).V2D();
-
-  switch (Op->Selector) {
-  case 0b00000000:
-    pmull(Dst, Src1, Src2);
-    break;
-  case 0b00000001:
-    mov(VTMP1.V1D(), Src1, 1);
-    pmull(Dst, VTMP1.V2D(), Src2);
-    break;
-  case 0b00010000:
-    mov(VTMP1.V1D(), Src2, 1);
-    pmull(Dst, VTMP1.V2D(), Src1);
-    break;
-  case 0b00010001:
-    pmull2(Dst, Src1, Src2);
-    break;
-  default:
-    LOGMAN_MSG_A_FMT("Unknown PCLMUL selector: {}", Op->Selector);
-    break;
-  }
-}
-
-#undef DEF_OP
-void Arm64JITCore::RegisterEncryptionHandlers() {
-#define REGISTER_OP(op, x) OpHandlers[FEXCore::IR::IROps::OP_##op] = &Arm64JITCore::Op_##x
-  REGISTER_OP(VAESIMC,           AESImc);
-  REGISTER_OP(VAESENC,           AESEnc);
-  REGISTER_OP(VAESENCLAST,       AESEncLast);
-  REGISTER_OP(VAESDEC,           AESDec);
-  REGISTER_OP(VAESDECLAST,       AESDecLast);
-  REGISTER_OP(VAESKEYGENASSIST,  AESKeyGenAssist);
-  REGISTER_OP(CRC32,             CRC32);
-  REGISTER_OP(PCLMUL,            PCLMUL);
-#undef REGISTER_OP
-}
-}
@@ -1,26 +0,0 @@
-/*
-$info$
-tags: backend|arm64
-$end_info$
-*/
-
-#include "Interface/Core/JIT/Arm64/JITClass.h"
-
-namespace FEXCore::CPU {
-
-using namespace vixl;
-using namespace vixl::aarch64;
-#define DEF_OP(x) void Arm64JITCore::Op_##x(IR::IROp_Header *IROp, IR::NodeID Node)
-DEF_OP(GetHostFlag) {
-  auto Op = IROp->C<IR::IROp_GetHostFlag>();
-  ubfx(GetReg<RA_64>(Node), GetReg<RA_64>(Op->Value.ID()), Op->Flag, 1);
-}
-
-#undef DEF_OP
-void Arm64JITCore::RegisterFlagHandlers() {
-#define REGISTER_OP(op, x) OpHandlers[FEXCore::IR::IROps::OP_##op] = &Arm64JITCore::Op_##x
-  REGISTER_OP(GETHOSTFLAG, GetHostFlag);
-#undef REGISTER_OP
-}
-}
-
@@ -1,891 +0,0 @@
-/*
-$info$
-glossary: Splatter ~ a code generator backend that concaternates configurable macros instead of doing isel
-glossary: IR ~ Intermediate Representation, our high-level opcode representation, loosely modeling arm64
-glossary: SSA ~ Single Static Assignment, a form of representing IR in memory
-glossary: Basic Block ~ A block of instructions with no control flow, terminated by control flow
-glossary: Fragment ~ A Collection of basic blocks, possibly an entire guest function or a subset of it
-tags: backend|arm64
-desc: Main glue logic of the arm64 splatter backend
-$end_info$
-*/
-
-#include "Interface/Context/Context.h"
-#include "Interface/Core/LookupCache.h"
-
-#include "Interface/Core/ArchHelpers/Arm64.h"
-#include "Interface/Core/ArchHelpers/MContext.h"
-#include "Interface/Core/Dispatcher/Arm64Dispatcher.h"
-#include "Interface/Core/JIT/Arm64/JITClass.h"
-#include "Interface/Core/InternalThreadState.h"
-
-#include "Interface/IR/Passes/RegisterAllocationPass.h"
-
-#include "Utils/MemberFunctionToPointer.h"
-
-#include <FEXCore/Core/X86Enums.h>
-#include <FEXCore/Core/UContext.h>
-#include <FEXCore/Utils/Allocator.h>
-#include <FEXCore/Utils/CompilerDefs.h>
-#include <FEXCore/Utils/EnumUtils.h>
-#include <FEXCore/Utils/Profiler.h>
-
-#include "Interface/Core/Interpreter/InterpreterOps.h"
-
-#include <sys/mman.h>
-#include <stdio.h>
-#include <unistd.h>
-#include <string.h>
-
-static constexpr size_t INITIAL_CODE_SIZE = 1024 * 1024 * 16;
-// We don't want to move above 128MB atm because that means we will have to encode longer jumps
-static constexpr size_t MAX_CODE_SIZE = 1024 * 1024 * 128;
-
-namespace {
-static uint64_t LUDIV(uint64_t SrcHigh, uint64_t SrcLow, uint64_t Divisor) {
-  __uint128_t Source = (static_cast<__uint128_t>(SrcHigh) << 64) | SrcLow;
-  __uint128_t Res = Source / Divisor;
-  return Res;
-}
-
-static int64_t LDIV(int64_t SrcHigh, int64_t SrcLow, int64_t Divisor) {
-  __int128_t Source = (static_cast<__int128_t>(SrcHigh) << 64) | SrcLow;
-  __int128_t Res = Source / Divisor;
-  return Res;
-}
-
-static uint64_t LUREM(uint64_t SrcHigh, uint64_t SrcLow, uint64_t Divisor) {
-  __uint128_t Source = (static_cast<__uint128_t>(SrcHigh) << 64) | SrcLow;
-  __uint128_t Res = Source % Divisor;
-  return Res;
-}
-
-static int64_t LREM(int64_t SrcHigh, int64_t SrcLow, int64_t Divisor) {
-  __int128_t Source = (static_cast<__int128_t>(SrcHigh) << 64) | SrcLow;
-  __int128_t Res = Source % Divisor;
-  return Res;
-}
-
-static void PrintValue(uint64_t Value) {
-  LogMan::Msg::DFmt("Value: 0x{:x}", Value);
-}
-
-static void PrintVectorValue(uint64_t Value, uint64_t ValueUpper) {
-  LogMan::Msg::DFmt("Value: 0x{:016x}'{:016x}", ValueUpper, Value);
-}
-}
-
-namespace FEXCore::CPU {
-
-using namespace vixl;
-using namespace vixl::aarch64;
-
-void Arm64JITCore::Op_Unhandled(IR::IROp_Header *IROp, IR::NodeID Node) {
-  FallbackInfo Info;
-  if (!InterpreterOps::GetFallbackHandler(IROp, &Info)) {
-#if defined(ASSERTIONS_ENABLED) && ASSERTIONS_ENABLED
-    LOGMAN_MSG_A_FMT("Unhandled IR Op: {}", FEXCore::IR::GetName(IROp->Op));
-#endif
-  } else {
-    switch(Info.ABI) {
-      case FABI_VOID_U16:{
-        SpillStaticRegs();
-
-        PushDynamicRegsAndLR();
-
-        uxth(w0, GetReg<RA_32>(IROp->Args[0].ID()));
-        ldr(x1, MemOperand(STATE, offsetof(FEXCore::Core::CpuStateFrame, Pointers.Common.FallbackHandlerPointers[Info.HandlerIndex])));
-
-#ifdef VIXL_SIMULATOR
-        GenerateIndirectRuntimeCall<void, uint16_t>(x1);
-#else
-        blr(x1);
-#endif
-
-        PopDynamicRegsAndLR();
-
-        FillStaticRegs();
-      }
-      break;
-
-      case FABI_F80_F32:{
-        SpillStaticRegs();
-
-        PushDynamicRegsAndLR();
-
-        fmov(v0.S(), GetSrc(IROp->Args[0].ID()).S()) ;
-        ldr(x0, MemOperand(STATE, offsetof(FEXCore::Core::CpuStateFrame, Pointers.Common.FallbackHandlerPointers[Info.HandlerIndex])));
-#ifdef VIXL_SIMULATOR
-        GenerateIndirectRuntimeCall<__uint128_t, float>(x0);
-#else
-        blr(x0);
-#endif
-
-        PopDynamicRegsAndLR();
-
-        FillStaticRegs();
-
-        eor(GetDst(Node).V16B(), GetDst(Node).V16B(), GetDst(Node).V16B());
-        ins(GetDst(Node).V2D(), 0, x0);
-        ins(GetDst(Node).V8H(), 4, w1);
-      }
-      break;
-
-      case FABI_F80_F64:{
-        SpillStaticRegs();
-
-        PushDynamicRegsAndLR();
-
-        mov(v0.D(), GetSrc(IROp->Args[0].ID()).D());
-        ldr(x0, MemOperand(STATE, offsetof(FEXCore::Core::CpuStateFrame, Pointers.Common.FallbackHandlerPointers[Info.HandlerIndex])));
-#ifdef VIXL_SIMULATOR
-        GenerateIndirectRuntimeCall<__uint128_t, double>(x0);
-#else
-        blr(x0);
-#endif
-
-        PopDynamicRegsAndLR();
-
-        FillStaticRegs();
-
-        eor(GetDst(Node).V16B(), GetDst(Node).V16B(), GetDst(Node).V16B());
-        ins(GetDst(Node).V2D(), 0, x0);
-        ins(GetDst(Node).V8H(), 4, w1);
-      }
-      break;
-
-      case FABI_F80_I16:
-      case FABI_F80_I32: {
-        SpillStaticRegs();
-
-        PushDynamicRegsAndLR();
-
-        if (Info.ABI == FABI_F80_I16) {
-          uxth(w0, GetReg<RA_32>(IROp->Args[0].ID()));
-        }
-        else {
-          mov(w0, GetReg<RA_32>(IROp->Args[0].ID()));
-        }
-        ldr(x1, MemOperand(STATE, offsetof(FEXCore::Core::CpuStateFrame, Pointers.Common.FallbackHandlerPointers[Info.HandlerIndex])));
-#ifdef VIXL_SIMULATOR
-        GenerateIndirectRuntimeCall<__uint128_t, uint32_t>(x1);
-#else
-        blr(x1);
-#endif
-
-        PopDynamicRegsAndLR();
-
-        FillStaticRegs();
-
-        eor(GetDst(Node).V16B(), GetDst(Node).V16B(), GetDst(Node).V16B());
-        ins(GetDst(Node).V2D(), 0, x0);
-        ins(GetDst(Node).V8H(), 4, w1);
-      }
-      break;
-
-      case FABI_F32_F80:{
-        SpillStaticRegs();
-
-        PushDynamicRegsAndLR();
-
-        umov(x0, GetSrc(IROp->Args[0].ID()).V2D(), 0);
-        umov(w1, GetSrc(IROp->Args[0].ID()).V8H(), 4);
-
-        ldr(x2, MemOperand(STATE, offsetof(FEXCore::Core::CpuStateFrame, Pointers.Common.FallbackHandlerPointers[Info.HandlerIndex])));
-#ifdef VIXL_SIMULATOR
-        GenerateIndirectRuntimeCall<float, uint64_t, uint64_t>(x2);
-#else
-        blr(x2);
-#endif
-
-        PopDynamicRegsAndLR();
-
-        FillStaticRegs();
-
-        fmov(GetDst(Node).S(), v0.S());
-      }
-      break;
-
-      case FABI_F64_F80:{
-        SpillStaticRegs();
-
-        PushDynamicRegsAndLR();
-
-        umov(x0, GetSrc(IROp->Args[0].ID()).V2D(), 0);
-        umov(w1, GetSrc(IROp->Args[0].ID()).V8H(), 4);
-
-        ldr(x2, MemOperand(STATE, offsetof(FEXCore::Core::CpuStateFrame, Pointers.Common.FallbackHandlerPointers[Info.HandlerIndex])));
-#ifdef VIXL_SIMULATOR
-        GenerateIndirectRuntimeCall<double, uint64_t, uint64_t>(x2);
-#else
-        blr(x2);
-#endif
-
-        PopDynamicRegsAndLR();
-
-        FillStaticRegs();
-
-        mov(GetDst(Node).D(), v0.D());
-      }
-      break;
-
-      case FABI_F64_F64: {
-        SpillStaticRegs();
-
-        PushDynamicRegsAndLR();
-
-        mov(v0.D(), GetSrc(IROp->Args[0].ID()).D());
-        ldr(x0, MemOperand(STATE, offsetof(FEXCore::Core::CpuStateFrame, Pointers.Common.FallbackHandlerPointers[Info.HandlerIndex])));
-#ifdef VIXL_SIMULATOR
-        GenerateIndirectRuntimeCall<double, double>(x0);
-#else
-        blr(x0);
-#endif
-
-        PopDynamicRegsAndLR();
-
-        FillStaticRegs();
-
-        mov(GetDst(Node).D(), v0.D());
-
-      }
-      break;
-
-      case FABI_F64_F64_F64: {
-        SpillStaticRegs();
-
-        PushDynamicRegsAndLR();
-
-        mov(v0.D(), GetSrc(IROp->Args[0].ID()).D());
-        mov(v1.D(), GetSrc(IROp->Args[1].ID()).D());
-        ldr(x0, MemOperand(STATE, offsetof(FEXCore::Core::CpuStateFrame, Pointers.Common.FallbackHandlerPointers[Info.HandlerIndex])));
-#ifdef VIXL_SIMULATOR
-        GenerateIndirectRuntimeCall<double, double, double>(x0);
-#else
-        blr(x0);
-#endif
-
-        PopDynamicRegsAndLR();
-
-        FillStaticRegs();
-
-        mov(GetDst(Node).D(), v0.D());
-
-      }
-      break;
-
-      case FABI_I16_F80:{
-        SpillStaticRegs();
-
-        PushDynamicRegsAndLR();
-
-        umov(x0, GetSrc(IROp->Args[0].ID()).V2D(), 0);
-        umov(w1, GetSrc(IROp->Args[0].ID()).V8H(), 4);
-
-        ldr(x2, MemOperand(STATE, offsetof(FEXCore::Core::CpuStateFrame, Pointers.Common.FallbackHandlerPointers[Info.HandlerIndex])));
-#ifdef VIXL_SIMULATOR
-        GenerateIndirectRuntimeCall<uint32_t, uint64_t, uint64_t>(x2);
-#else
-        blr(x2);
-#endif
-
-        PopDynamicRegsAndLR();
-
-        FillStaticRegs();
-
-        uxth(GetReg<RA_64>(Node), x0);
-      }
-      break;
-      case FABI_I32_F80:{
-        SpillStaticRegs();
-
-        PushDynamicRegsAndLR();
-
-        umov(x0, GetSrc(IROp->Args[0].ID()).V2D(), 0);
-        umov(w1, GetSrc(IROp->Args[0].ID()).V8H(), 4);
-
-        ldr(x2, MemOperand(STATE, offsetof(FEXCore::Core::CpuStateFrame, Pointers.Common.FallbackHandlerPointers[Info.HandlerIndex])));
-#ifdef VIXL_SIMULATOR
-        GenerateIndirectRuntimeCall<uint32_t, uint64_t, uint64_t>(x2);
-#else
-        blr(x2);
-#endif
-
-        PopDynamicRegsAndLR();
-
-        FillStaticRegs();
-
-        mov(GetReg<RA_32>(Node), w0);
-      }
-      break;
-      case FABI_I64_F80:{
-        SpillStaticRegs();
-
-        PushDynamicRegsAndLR();
-
-        umov(x0, GetSrc(IROp->Args[0].ID()).V2D(), 0);
-        umov(w1, GetSrc(IROp->Args[0].ID()).V8H(), 4);
-
-        ldr(x2, MemOperand(STATE, offsetof(FEXCore::Core::CpuStateFrame, Pointers.Common.FallbackHandlerPointers[Info.HandlerIndex])));
-#ifdef VIXL_SIMULATOR
-        GenerateIndirectRuntimeCall<uint64_t, uint64_t, uint64_t>(x2);
-#else
-        blr(x2);
-#endif
-
-        PopDynamicRegsAndLR();
-
-        FillStaticRegs();
-
-        mov(GetReg<RA_64>(Node), x0);
-      }
-      break;
-      case FABI_I64_F80_F80:{
-        SpillStaticRegs();
-
-        PushDynamicRegsAndLR();
-
-        umov(x0, GetSrc(IROp->Args[0].ID()).V2D(), 0);
-        umov(w1, GetSrc(IROp->Args[0].ID()).V8H(), 4);
-
-        umov(x2, GetSrc(IROp->Args[1].ID()).V2D(), 0);
-        umov(w3, GetSrc(IROp->Args[1].ID()).V8H(), 4);
-
-        ldr(x4, MemOperand(STATE, offsetof(FEXCore::Core::CpuStateFrame, Pointers.Common.FallbackHandlerPointers[Info.HandlerIndex])));
-#ifdef VIXL_SIMULATOR
-        GenerateIndirectRuntimeCall<uint64_t, uint64_t, uint64_t, uint64_t, uint64_t>(x4);
-#else
-        blr(x4);
-#endif
-        PopDynamicRegsAndLR();
-
-        FillStaticRegs();
-
-        mov(GetReg<RA_64>(Node), x0);
-      }
-      break;
-      case FABI_F80_F80:{
-        SpillStaticRegs();
-
-        PushDynamicRegsAndLR();
-
-        umov(x0, GetSrc(IROp->Args[0].ID()).V2D(), 0);
-        umov(w1, GetSrc(IROp->Args[0].ID()).V8H(), 4);
-
-        ldr(x2, MemOperand(STATE, offsetof(FEXCore::Core::CpuStateFrame, Pointers.Common.FallbackHandlerPointers[Info.HandlerIndex])));
-#ifdef VIXL_SIMULATOR
-        GenerateIndirectRuntimeCall<__uint128_t, uint64_t, uint64_t>(x2);
-#else
-        blr(x2);
-#endif
-
-        PopDynamicRegsAndLR();
-
-        FillStaticRegs();
-
-        eor(GetDst(Node).V16B(), GetDst(Node).V16B(), GetDst(Node).V16B());
-        ins(GetDst(Node).V2D(), 0, x0);
-        ins(GetDst(Node).V8H(), 4, w1);
-      }
-      break;
-      case FABI_F80_F80_F80:{
-        SpillStaticRegs();
-
-        PushDynamicRegsAndLR();
-
-        umov(x0, GetSrc(IROp->Args[0].ID()).V2D(), 0);
-        umov(w1, GetSrc(IROp->Args[0].ID()).V8H(), 4);
-
-        umov(x2, GetSrc(IROp->Args[1].ID()).V2D(), 0);
-        umov(w3, GetSrc(IROp->Args[1].ID()).V8H(), 4);
-
-        ldr(x4, MemOperand(STATE, offsetof(FEXCore::Core::CpuStateFrame, Pointers.Common.FallbackHandlerPointers[Info.HandlerIndex])));
-#ifdef VIXL_SIMULATOR
-        GenerateIndirectRuntimeCall<__uint128_t, uint64_t, uint64_t, uint64_t, uint64_t>(x4);
-#else
-        blr(x4);
-#endif
-
-        PopDynamicRegsAndLR();
-
-        FillStaticRegs();
-
-        eor(GetDst(Node).V16B(), GetDst(Node).V16B(), GetDst(Node).V16B());
-        ins(GetDst(Node).V2D(), 0, x0);
-        ins(GetDst(Node).V8H(), 4, w1);
-      }
-      break;
-
-      case FABI_UNKNOWN:
-      default:
-#if defined(ASSERTIONS_ENABLED) && ASSERTIONS_ENABLED
-        LOGMAN_MSG_A_FMT("Unhandled IR Fallback ABI: {} {}",
-                         FEXCore::IR::GetName(IROp->Op), ToUnderlying(Info.ABI));
-#endif
-      break;
-    }
-  }
-}
-
-
-static uint64_t Arm64JITCore_ExitFunctionLink(FEXCore::Core::CpuStateFrame *Frame, uint64_t *record) {
-  auto Thread = Frame->Thread;
-  auto GuestRip = record[1];
-
-  auto HostCode = Thread->LookupCache->FindBlock(GuestRip);
-
-  if (!HostCode) {
-    //fmt::print("ExitFunctionLink: Aborting, {:X} not in cache\n", GuestRip);
-    Frame->State.rip = GuestRip;
-    return Frame->Pointers.Common.DispatcherLoopTop;
-  }
-
-  uintptr_t branch = (uintptr_t)(record) - 8;
-  auto LinkerAddress = Frame->Pointers.Common.ExitFunctionLinker;
-
-  auto offset = HostCode/4 - branch/4;
-  if (IsInt26(offset)) {
-    // optimal case - can branch directly
-    // patch the code
-    vixl::aarch64::Assembler emit((uint8_t*)(branch), 24);
-    vixl::CodeBufferCheckScope scope(&emit, 24, vixl::CodeBufferCheckScope::kDontReserveBufferSpace, vixl::CodeBufferCheckScope::kNoAssert);
-    emit.b(offset);
-    emit.FinalizeCode();
-    vixl::aarch64::CPU::EnsureIAndDCacheCoherency((void*)branch, 24);
-
-    // Add de-linking handler
-    Context::Context::ThreadAddBlockLink(Thread, GuestRip, (uintptr_t)record, [branch, LinkerAddress]{
-      vixl::aarch64::Assembler emit((uint8_t*)(branch), 24);
-      vixl::CodeBufferCheckScope scope(&emit, 24, vixl::CodeBufferCheckScope::kDontReserveBufferSpace, vixl::CodeBufferCheckScope::kNoAssert);
-      Literal l_BranchHost{LinkerAddress};
-      emit.ldr(x0, &l_BranchHost);
-      emit.blr(x0);
-      emit.place(&l_BranchHost);
-      emit.FinalizeCode();
-      vixl::aarch64::CPU::EnsureIAndDCacheCoherency((void*)branch, 24);
-    });
-  } else {
-    // fallback case - do a soft-er link by patching the pointer
-    record[0] = HostCode;
-
-    // Add de-linking handler
-    Context::Context::ThreadAddBlockLink(Thread, GuestRip, (uintptr_t)record, [record, LinkerAddress]{
-      record[0] = LinkerAddress;
-    });
-  }
-
-  return HostCode;
-}
-
-void Arm64JITCore::Op_NoOp(IR::IROp_Header *IROp, IR::NodeID Node) {
-}
-
-Arm64JITCore::Arm64JITCore(FEXCore::Context::Context *ctx, FEXCore::Core::InternalThreadState *Thread)
-  : CPUBackend(Thread, INITIAL_CODE_SIZE, MAX_CODE_SIZE)
-  , Arm64Emitter(ctx, 0)
-  , HostSupportsSVE{ctx->HostFeatures.SupportsAVX}
-  , CTX {ctx} {
-
-  RAPass = Thread->PassManager->GetPass<IR::RegisterAllocationPass>("RA");
-
-#if DEBUG
-  Decoder.AppendVisitor(&Disasm)
-#endif
-
-  uint32_t NumUsedGPRs = NumGPRs;
-  uint32_t NumUsedGPRPairs = NumGPRPairs;
-  uint32_t UsedRegisterCount = RegisterCount;
-
-  RAPass->AllocateRegisterSet(UsedRegisterCount, RegisterClasses);
-
-  RAPass->AddRegisters(FEXCore::IR::GPRClass, NumUsedGPRs);
-  RAPass->AddRegisters(FEXCore::IR::GPRFixedClass, SRA64.size());
-  RAPass->AddRegisters(FEXCore::IR::FPRClass, NumFPRs);
-  RAPass->AddRegisters(FEXCore::IR::FPRFixedClass, SRAFPR.size()  );
-  RAPass->AddRegisters(FEXCore::IR::GPRPairClass, NumUsedGPRPairs);
-  RAPass->AddRegisters(FEXCore::IR::ComplexClass, 1);
-
-  for (uint32_t i = 0; i < NumUsedGPRPairs; ++i) {
-    RAPass->AddRegisterConflict(FEXCore::IR::GPRClass, i * 2,     FEXCore::IR::GPRPairClass, i);
-    RAPass->AddRegisterConflict(FEXCore::IR::GPRClass, i * 2 + 1, FEXCore::IR::GPRPairClass, i);
-  }
-
-  for (uint32_t i = 0; i < FEXCore::IR::IROps::OP_LAST + 1; ++i) {
-    OpHandlers[i] = &Arm64JITCore::Op_Unhandled;
-  }
-
-  RegisterALUHandlers();
-  RegisterAtomicHandlers();
-  RegisterBranchHandlers();
-  RegisterConversionHandlers();
-  RegisterFlagHandlers();
-  RegisterMemoryHandlers();
-  RegisterMiscHandlers();
-  RegisterMoveHandlers();
-  RegisterVectorHandlers();
-  RegisterEncryptionHandlers();
-
-  {
-    // Set up pointers that the JIT needs to load
-
-    // Common
-    auto &Common = ThreadState->CurrentFrame->Pointers.Common;
-
-    Common.PrintValue = reinterpret_cast<uint64_t>(PrintValue);
-    Common.PrintVectorValue = reinterpret_cast<uint64_t>(PrintVectorValue);
-    Common.ThreadRemoveCodeEntryFromJIT = reinterpret_cast<uintptr_t>(&Context::Context::ThreadRemoveCodeEntryFromJit);
-    Common.CPUIDObj = reinterpret_cast<uint64_t>(&CTX->CPUID);
-
-    {
-      FEXCore::Utils::MemberFunctionToPointerCast PMF(&FEXCore::CPUIDEmu::RunFunction);
-      Common.CPUIDFunction = PMF.GetConvertedPointer();
-    }
-
-    Common.SyscallHandlerObj = reinterpret_cast<uint64_t>(CTX->SyscallHandler);
-    Common.SyscallHandlerFunc = reinterpret_cast<uint64_t>(FEXCore::Context::HandleSyscall);
-    Common.ExitFunctionLink = reinterpret_cast<uintptr_t>(&Context::Context::ThreadExitFunctionLink<Arm64JITCore_ExitFunctionLink>);
-
-
-    // Fill in the fallback handlers
-    InterpreterOps::FillFallbackIndexPointers(Common.FallbackHandlerPointers);
-
-    // Platform Specific
-    auto &AArch64 = ThreadState->CurrentFrame->Pointers.AArch64;
-
-    AArch64.LUDIV = reinterpret_cast<uint64_t>(LUDIV);
-    AArch64.LDIV = reinterpret_cast<uint64_t>(LDIV);
-    AArch64.LUREM = reinterpret_cast<uint64_t>(LUREM);
-    AArch64.LREM = reinterpret_cast<uint64_t>(LREM);
-  }
-
-  // Must be done after Dispatcher init
-  SetAllowAssembler(true);
-  ClearCache();
-}
-
-void Arm64JITCore::InitializeSignalHandlers(FEXCore::Context::Context *CTX) {
-  CTX->SignalDelegation->RegisterHostSignalHandler(SIGILL, [](FEXCore::Core::InternalThreadState *Thread, int Signal, void *info, void *ucontext) -> bool {
-    return Thread->CTX->Dispatcher->HandleSIGILL(Thread, Signal, info, ucontext);
-  }, true);
-
-#ifdef _M_ARM_64
-  CTX->SignalDelegation->RegisterHostSignalHandler(SIGBUS, [](FEXCore::Core::InternalThreadState *Thread, int Signal, void *info, void *ucontext) -> bool {
-    if (!Thread->CPUBackend->IsAddressInCodeBuffer(ArchHelpers::Context::GetPc(ucontext))) {
-      // Wasn't a sigbus in JIT code
-      return false;
-    }
-
-    return FEXCore::ArchHelpers::Arm64::HandleSIGBUS(Thread->CTX->Config.ParanoidTSO(), Signal, info, ucontext);
-  }, true);
-#endif
-}
-
-void Arm64JITCore::EmitDetectionString() {
-  const char JITString[] = "FEXJIT::Arm64JITCore::";
-  auto Buffer = GetBuffer();
-  Buffer->EmitString(JITString);
-  Buffer->Align();
-}
-
-void Arm64JITCore::ClearCache() {
-  // Get the backing code buffer
-
-  auto CodeBuffer = GetEmptyCodeBuffer();
-  *GetBuffer() = vixl::CodeBuffer(CodeBuffer->Ptr, CodeBuffer->Size);
-  EmitDetectionString();
-}
-
-Arm64JITCore::~Arm64JITCore() {
-
-}
-
-IR::PhysicalRegister Arm64JITCore::GetPhys(IR::NodeID Node) const {
-  auto PhyReg = RAData->GetNodeRegister(Node);
-
-  LOGMAN_THROW_A_FMT(!PhyReg.IsInvalid(), "Couldn't Allocate register for node: ssa{}. Class: {}", Node, PhyReg.Class);
-
-  return PhyReg;
-}
-
-template<>
-aarch64::Register Arm64JITCore::GetReg<Arm64JITCore::RA_32>(IR::NodeID Node) const {
-  auto Reg = GetPhys(Node);
-
-  LOGMAN_THROW_AA_FMT(Reg.Class == IR::GPRFixedClass.Val || Reg.Class == IR::GPRClass.Val, "Unexpected Class: {}", Reg.Class);
-
-  if (Reg.Class == IR::GPRFixedClass.Val) {
-    return SRA64[Reg.Reg].W();
-  } else if (Reg.Class == IR::GPRClass.Val) {
-    return RA64[Reg.Reg].W();
-  }
-
-  FEX_UNREACHABLE;
-}
-
-template<>
-aarch64::Register Arm64JITCore::GetReg<Arm64JITCore::RA_64>(IR::NodeID Node) const {
-  auto Reg = GetPhys(Node);
-
-  LOGMAN_THROW_AA_FMT(Reg.Class == IR::GPRFixedClass.Val || Reg.Class == IR::GPRClass.Val, "Unexpected Class: {}", Reg.Class);
-
-  if (Reg.Class == IR::GPRFixedClass.Val) {
-    return SRA64[Reg.Reg];
-  } else if (Reg.Class == IR::GPRClass.Val) {
-    return RA64[Reg.Reg];
-  }
-
-  FEX_UNREACHABLE;
-}
-
-template<>
-std::pair<aarch64::Register, aarch64::Register> Arm64JITCore::GetSrcPair<Arm64JITCore::RA_32>(IR::NodeID Node) const {
-  uint32_t Reg = GetPhys(Node).Reg;
-  return RA32Pair[Reg];
-}
-
-template<>
-std::pair<aarch64::Register, aarch64::Register> Arm64JITCore::GetSrcPair<Arm64JITCore::RA_64>(IR::NodeID Node) const {
-  uint32_t Reg = GetPhys(Node).Reg;
-  return RA64Pair[Reg];
-}
-
-aarch64::VRegister Arm64JITCore::GetSrc(IR::NodeID Node) const {
-  auto Reg = GetPhys(Node);
-
-  LOGMAN_THROW_AA_FMT(Reg.Class == IR::FPRFixedClass.Val || Reg.Class == IR::FPRClass.Val, "Unexpected Class: {}", Reg.Class);
-
-  if (Reg.Class == IR::FPRFixedClass.Val) {
-    return SRAFPR[Reg.Reg];
-  } else if (Reg.Class == IR::FPRClass.Val) {
-    return RAFPR[Reg.Reg];
-  }
-
-  FEX_UNREACHABLE;
-}
-
-aarch64::VRegister Arm64JITCore::GetDst(IR::NodeID Node) const {
-  auto Reg = GetPhys(Node);
-
-  LOGMAN_THROW_AA_FMT(Reg.Class == IR::FPRFixedClass.Val || Reg.Class == IR::FPRClass.Val, "Unexpected Class: {}", Reg.Class);
-
-  if (Reg.Class == IR::FPRFixedClass.Val) {
-    return SRAFPR[Reg.Reg];
-  } else if (Reg.Class == IR::FPRClass.Val) {
-    return RAFPR[Reg.Reg];
-  }
-
-  FEX_UNREACHABLE;
-}
-
-bool Arm64JITCore::IsInlineConstant(const IR::OrderedNodeWrapper& WNode, uint64_t* Value) const {
-  auto OpHeader = IR->GetOp<IR::IROp_Header>(WNode);
-
-  if (OpHeader->Op == IR::IROps::OP_INLINECONSTANT) {
-    auto Op = OpHeader->C<IR::IROp_InlineConstant>();
-    if (Value) {
-      *Value = Op->Constant;
-    }
-    return true;
-  } else {
-    return false;
-  }
-}
-
-bool Arm64JITCore::IsInlineEntrypointOffset(const IR::OrderedNodeWrapper& WNode, uint64_t* Value) const {
-  auto OpHeader = IR->GetOp<IR::IROp_Header>(WNode);
-
-  if (OpHeader->Op == IR::IROps::OP_INLINEENTRYPOINTOFFSET) {
-    auto Op = OpHeader->C<IR::IROp_InlineEntrypointOffset>();
-    if (Value) {
-      uint64_t Mask = ~0ULL;
-      uint8_t OpSize = OpHeader->Size;
-      if (OpSize == 4) {
-        Mask = 0xFFFF'FFFFULL;
-      }
-      *Value = (Entry + Op->Offset) & Mask;
-    }
-    return true;
-  } else {
-    return false;
-  }
-}
-
-FEXCore::IR::RegisterClassType Arm64JITCore::GetRegClass(IR::NodeID Node) const {
-  return FEXCore::IR::RegisterClassType {GetPhys(Node).Class};
-}
-
-
-bool Arm64JITCore::IsFPR(IR::NodeID Node) const {
-  auto Class = GetRegClass(Node);
-
-  return Class == IR::FPRClass || Class == IR::FPRFixedClass;
-}
-
-bool Arm64JITCore::IsGPR(IR::NodeID Node) const {
-  auto Class = GetRegClass(Node);
-
-  return Class == IR::GPRClass || Class == IR::GPRFixedClass;
-}
-
-void *Arm64JITCore::CompileCode(uint64_t Entry,
-                                FEXCore::IR::IRListView const *IR,
-                                FEXCore::Core::DebugData *DebugData,
-                                FEXCore::IR::RegisterAllocationData *RAData,
-                                bool GDBEnabled) {
-  FEXCORE_PROFILE_SCOPED("Arm64::CompileCode");
-
-  using namespace aarch64;
-  JumpTargets.clear();
-  uint32_t SSACount = IR->GetSSACount();
-
-  this->Entry = Entry;
-  this->RAData = RAData;
-  this->DebugData = DebugData;
-
-  #ifndef NDEBUG
-  LoadConstant(x0, Entry);
-  #endif
-
-  this->IR = IR;
-
-  // Fairly excessive buffer range to make sure we don't overflow
-  uint32_t BufferRange = SSACount * 16 + GDBEnabled * Dispatcher::MaxGDBPauseCheckSize;
-  if ((GetCursorOffset() + BufferRange) > CurrentCodeBuffer->Size) {
-    CTX->ClearCodeCache(ThreadState);
-  }
-
-  // AAPCS64
-  // r30      = LR
-  // r29      = FP
-  // r19..r28 = Callee saved
-  // r18      = Platform Register (Matters if we target Windows or iOS)
-  // r16..r17 = Inter-procedure scratch
-  //  r9..r15 = Temp
-  //  r8      = Indirect Result
-  //  r0...r7 = Parameter/Results
-  //
-  //  FPRS:
-  //  v8..v15 = (lower 64bits) Callee saved
-
-  // Our allocation:
-  // X0 = ThreadState
-  // X1 = MemBase
-  //
-  // X1-X3 = Temp
-  // X4-r18 = RA
-
-  GuestEntry = GetCursorAddress<uint8_t *>();
-
-  if (GDBEnabled) {
-    auto GDBSize = CTX->Dispatcher->GenerateGDBPauseCheck(GuestEntry, Entry);
-    GetBuffer()->CursorForward(GDBSize);
-  }
-
-  //LOGMAN_THROW_A_FMT(RAData->HasFullRA(), "Arm64 JIT only works with RA");
-
-  SpillSlots = RAData->SpillSlots();
-
-  if (SpillSlots) {
-    const auto TotalSpillSlotsSize = SpillSlots * MaxSpillSlotSize;
-
-    if (IsImmAddSub(TotalSpillSlotsSize)) {
-      sub(sp, sp, TotalSpillSlotsSize);
-    } else {
-      LoadConstant(x0, TotalSpillSlotsSize);
-      sub(sp, sp, x0);
-    }
-  }
-
-  PendingTargetLabel = nullptr;
-
-  for (auto [BlockNode, BlockHeader] : IR->GetBlocks()) {
-    using namespace FEXCore::IR;
-#if defined(ASSERTIONS_ENABLED) && ASSERTIONS_ENABLED
-    auto BlockIROp = BlockHeader->CW<FEXCore::IR::IROp_CodeBlock>();
-    LOGMAN_THROW_AA_FMT(BlockIROp->Header.Op == IR::OP_CODEBLOCK, "IR type failed to be a code block");
-#endif
-
-    auto BlockStartHostCode = GetCursorAddress<uint8_t *>();
-    {
-      const auto Node = IR->GetID(BlockNode);
-      const auto IsTarget = JumpTargets.try_emplace(Node).first;
-
-      // if there's a pending branch, and it is not fall-through
-      if (PendingTargetLabel && PendingTargetLabel != &IsTarget->second)
-      {
-        b(PendingTargetLabel);
-      }
-      PendingTargetLabel = nullptr;
-
-      bind(&IsTarget->second);
-    }
-
-    for (auto [CodeNode, IROp] : IR->GetCode(BlockNode)) {
-      const auto ID = IR->GetID(CodeNode);
-
-      // Execute handler
-      OpHandler Handler = OpHandlers[IROp->Op];
-      (this->*Handler)(IROp, ID);
-    }
-
-    if (DebugData) {
-      DebugData->Subblocks.push_back({
-        static_cast<uint32_t>(BlockStartHostCode - GuestEntry),
-        static_cast<uint32_t>(GetCursorAddress<uint8_t *>() - BlockStartHostCode)
-      });
-    }
-  }
-
-  // Make sure last branch is generated. It certainly can't be eliminated here.
-  if (PendingTargetLabel)
-  {
-    b(PendingTargetLabel);
-  }
-  PendingTargetLabel = nullptr;
-
-  FinalizeCode();
-
-  auto CodeEnd = GetCursorAddress<uint8_t *>();
-  CPU.EnsureIAndDCacheCoherency(GuestEntry, CodeEnd - GuestEntry);
-
-  if (DebugData) {
-    DebugData->HostCodeSize = CodeEnd - GuestEntry;
-    DebugData->Relocations = &Relocations;
-  }
-
-  this->IR = nullptr;
-
-  return GuestEntry;
-}
-
-void Arm64JITCore::ResetStack() {
-  if (SpillSlots == 0) {
-    return;
-  }
-
-  const auto TotalSpillSlotsSize = SpillSlots * MaxSpillSlotSize;
-
-  if (IsImmAddSub(TotalSpillSlotsSize)) {
-    add(sp, sp, TotalSpillSlotsSize);
-  } else {
-   // Too big to fit in a 12bit immediate
-   LoadConstant(x0, TotalSpillSlotsSize);
-   add(sp, sp, x0);
-  }
-}
-
-std::unique_ptr<CPUBackend> CreateArm64JITCore(FEXCore::Context::Context *ctx, FEXCore::Core::InternalThreadState *Thread) {
-  return std::make_unique<Arm64JITCore>(ctx, Thread);
-}
-
-void InitializeArm64JITSignalHandlers(FEXCore::Context::Context *CTX) {
-  Arm64JITCore::InitializeSignalHandlers(CTX);
-}
-
-CPUBackendFeatures GetArm64JITBackendFeatures() {
-  return CPUBackendFeatures {
-    .SupportsStaticRegisterAllocation = true
-  };
-}
-
-}
@@ -1,257 +0,0 @@
-/*
-$info$
-tags: backend|arm64
-$end_info$
-*/
-
-#include <syscall.h>
-#include "Interface/Core/JIT/Arm64/JITClass.h"
-#include "FEXCore/Debug/InternalThreadState.h"
-
-namespace FEXCore::CPU {
-using namespace vixl;
-using namespace vixl::aarch64;
-#define DEF_OP(x) void Arm64JITCore::Op_##x(IR::IROp_Header *IROp, IR::NodeID Node)
-
-DEF_OP(GuestOpcode) {
-  auto Op = IROp->C<IR::IROp_GuestOpcode>();
-  // metadata
-  DebugData->GuestOpcodes.push_back({Op->GuestEntryOffset, GetCursorAddress<uint8_t*>() - GuestEntry});
-}
-
-DEF_OP(Fence) {
-  auto Op = IROp->C<IR::IROp_Fence>();
-  switch (Op->Fence) {
-    case IR::Fence_Load.Val:
-      dmb(FullSystem, BarrierReads);
-      break;
-    case IR::Fence_LoadStore.Val:
-      dmb(FullSystem, BarrierAll);
-      break;
-    case IR::Fence_Store.Val:
-      dmb(FullSystem, BarrierWrites);
-      break;
-    default: LOGMAN_MSG_A_FMT("Unknown Fence: {}", Op->Fence); break;
-  }
-}
-
-DEF_OP(Break) {
-  auto Op = IROp->C<IR::IROp_Break>();
-
-  // First we must reset the stack
-  ResetStack();
-
-  LoadConstant(w1, 1);
-  strb(w1, MemOperand(STATE, offsetof(FEXCore::Core::CpuStateFrame, SynchronousFaultData.FaultToTopAndGeneratedException)));
-  LoadConstant(w1, Op->Reason.Signal);
-  strb(w1, MemOperand(STATE, offsetof(FEXCore::Core::CpuStateFrame, SynchronousFaultData.Signal)));
-  LoadConstant(w1, Op->Reason.TrapNumber);
-  str(w1, MemOperand(STATE, offsetof(FEXCore::Core::CpuStateFrame, SynchronousFaultData.TrapNo)));
-  LoadConstant(w1, Op->Reason.si_code);
-  str(w1, MemOperand(STATE, offsetof(FEXCore::Core::CpuStateFrame, SynchronousFaultData.si_code)));
-  LoadConstant(x1, Op->Reason.ErrorRegister);
-  str(w1, MemOperand(STATE, offsetof(FEXCore::Core::CpuStateFrame, SynchronousFaultData.err_code)));
-
-  switch (Op->Reason.Signal) {
-  case SIGILL:
-    ldr(TMP1, MemOperand(STATE, offsetof(FEXCore::Core::CpuStateFrame, Pointers.Common.GuestSignal_SIGILL)));
-    br(TMP1);
-    break;
-  case SIGTRAP:
-    ldr(TMP1, MemOperand(STATE, offsetof(FEXCore::Core::CpuStateFrame, Pointers.Common.GuestSignal_SIGTRAP)));
-    br(TMP1);
-    break;
-  case SIGSEGV:
-    ldr(TMP1, MemOperand(STATE, offsetof(FEXCore::Core::CpuStateFrame, Pointers.Common.GuestSignal_SIGSEGV)));
-    br(TMP1);
-    break;
-  default:
-    ldr(TMP1, MemOperand(STATE, offsetof(FEXCore::Core::CpuStateFrame, Pointers.Common.GuestSignal_SIGTRAP)));
-    br(TMP1);
-    break;
-  }
-}
-
-DEF_OP(GetRoundingMode) {
-  auto Dst = GetReg<RA_64>(Node);
-  mrs(Dst, FPCR);
-  lsr(Dst, Dst,  22);
-
-  // FTZ is already in the correct location
-  // Rounding mode is different
-  and_(TMP1, Dst, 0b11);
-
-  cmp(TMP1, 1);
-  LoadConstant(TMP3, IR::ROUND_MODE_POSITIVE_INFINITY);
-  csel(TMP2, TMP3, xzr, vixl::aarch64::Condition::eq);
-
-  cmp(TMP1, 2);
-  LoadConstant(TMP3, IR::ROUND_MODE_NEGATIVE_INFINITY);
-  csel(TMP2, TMP3, TMP2, vixl::aarch64::Condition::eq);
-
-  cmp(TMP1, 3);
-  LoadConstant(TMP3, IR::ROUND_MODE_TOWARDS_ZERO);
-  csel(TMP2, TMP3, TMP2, vixl::aarch64::Condition::eq);
-
-  orr(Dst, Dst, TMP2);
-
-  bfi(Dst, TMP2, 0, 2);
-}
-
-DEF_OP(SetRoundingMode) {
-  auto Op = IROp->C<IR::IROp_SetRoundingMode>();
-  auto Src = GetReg<RA_64>(Op->RoundMode.ID());
-
-  // Setup the rounding flags correctly
-  and_(TMP1, Src, 0b11);
-
-  cmp(TMP1, IR::ROUND_MODE_POSITIVE_INFINITY);
-  LoadConstant(TMP3, 1);
-  csel(TMP2, TMP3, xzr, vixl::aarch64::Condition::eq);
-
-  cmp(TMP1, IR::ROUND_MODE_NEGATIVE_INFINITY);
-  LoadConstant(TMP3, 2);
-  csel(TMP2, TMP3, TMP2, vixl::aarch64::Condition::eq);
-
-  cmp(TMP1, IR::ROUND_MODE_TOWARDS_ZERO);
-  LoadConstant(TMP3, 3);
-  csel(TMP2, TMP3, TMP2, vixl::aarch64::Condition::eq);
-
-  mrs(TMP1, FPCR);
-
-  // vixl simulator doesn't support anything beyond ties-to-even rounding
-#ifndef VIXL_SIMULATOR
-  // Insert the rounding flags
-  bfi(TMP1, TMP2, 22, 2);
-#endif
-
-  // Insert the FTZ flag
-  lsr(TMP2, Src, 2);
-  bfi(TMP1, TMP2, 24, 1);
-
-  // Now save the new FPCR
-  msr(FPCR, TMP1);
-}
-
-DEF_OP(Print) {
-  auto Op = IROp->C<IR::IROp_Print>();
-
-  PushDynamicRegsAndLR();
-  SpillStaticRegs();
-
-  if (IsGPR(Op->Value.ID())) {
-    mov(x0, GetReg<RA_64>(Op->Value.ID()));
-    ldr(x3, MemOperand(STATE, offsetof(FEXCore::Core::CpuStateFrame, Pointers.Common.PrintValue)));
-  }
-  else {
-    fmov(x0, GetSrc(Op->Value.ID()).V1D());
-    // Bug in vixl that source vector needs to b V1D rather than V2D?
-    fmov(x1, GetSrc(Op->Value.ID()).V1D(), 1);
-    ldr(x3, MemOperand(STATE, offsetof(FEXCore::Core::CpuStateFrame, Pointers.Common.PrintVectorValue)));
-  }
-
-  blr(x3);
-
-  FillStaticRegs();
-  PopDynamicRegsAndLR();
-}
-
-DEF_OP(ProcessorID) {
-  // We always need to spill x8 since we can't know if it is live at this SSA location
-  uint32_t SpillMask = 1U << 8;
-
-  // Ordering is incredibly important here
-  // We must spill any overlapping registers first THEN claim we are in a syscall without invalidating state at all
-  // Only spill the registers that intersect with our usage
-  SpillStaticRegs(false, SpillMask);
-
-  // Now that we are spilled, store in the state that we are in a syscall
-  // Still without overwriting registers that matter
-  // 16bit LoadConstant to be a single instruction
-  // We must always spill at least one register (x8) so this value always has a bit set
-  // This gives the signal handler a value to check to see if we are in a syscall at all
-  LoadConstant(x0, SpillMask & 0xFFFF);
-  str(x0, MemOperand(STATE, offsetof(FEXCore::Core::CpuStateFrame, InSyscallInfo)));
-
-  // Allocate some temporary space for storing the uint32_t CPU and Node IDs
-  sub(sp, sp, 16);
-
-  // Load the getcpu syscall number
-  LoadConstant(x8, SYS_getcpu);
-
-  // CPU pointer in x0
-  add(x0, sp, 0);
-  // Node in x1
-  add(x1, sp, 4);
-
-  svc(0);
-  // On updated signal mask we can receive a signal RIGHT HERE
-
-  // Load the values returned by the kernel
-  ldp(w0, w1, MemOperand(sp));
-  // Deallocate stack space
-  sub(sp, sp, 16);
-
-  // Now that we are done in the syscall we need to carefully peel back the state
-  // First unspill the registers from before
-  FillStaticRegs(false, SpillMask);
-
-  // Now the registers we've spilled are back in their original host registers
-  // We can safely claim we are no longer in a syscall
-  str(xzr, MemOperand(STATE, offsetof(FEXCore::Core::CpuStateFrame, InSyscallInfo)));
-
-
-  // Now store the result in the destination in the expected format
-  // uint32_t Res = (node << 12) | cpu;
-  // CPU is in w0
-  // Node is in w1
-  orr(GetReg<RA_64>(Node), x0, Operand(x1, LSL, 12));
-}
-
-DEF_OP(RDRAND) {
-  auto Op = IROp->C<IR::IROp_RDRAND>();
-
-  // Results are in x0, x1
-  // Results want to be in a i64v2 vector
-  auto Dst = GetSrcPair<RA_64>(Node);
-
-  if (Op->GetReseeded) {
-    mrs(Dst.first, RNDRRS);
-  }
-  else {
-    mrs(Dst.first, RNDR);
-  }
-
-  // If the rng number is valid then NZCV is 0b0000, otherwise NZCV is 0b0100
-  cset(Dst.second, Condition::ne);
-}
-
-DEF_OP(Yield) {
-  hint(SystemHint::YIELD);
-}
-
-#undef DEF_OP
-void Arm64JITCore::RegisterMiscHandlers() {
-#define REGISTER_OP(op, x) OpHandlers[FEXCore::IR::IROps::OP_##op] = &Arm64JITCore::Op_##x
-  REGISTER_OP(DUMMY,      NoOp);
-  REGISTER_OP(IRHEADER,   NoOp);
-  REGISTER_OP(CODEBLOCK,  NoOp);
-  REGISTER_OP(BEGINBLOCK, NoOp);
-  REGISTER_OP(ENDBLOCK,   NoOp);
-  REGISTER_OP(GUESTOPCODE, GuestOpcode);
-  REGISTER_OP(FENCE,      Fence);
-  REGISTER_OP(BREAK,      Break);
-  REGISTER_OP(PHI,        NoOp);
-  REGISTER_OP(PHIVALUE,   NoOp);
-  REGISTER_OP(PRINT,      Print);
-  REGISTER_OP(GETROUNDINGMODE, GetRoundingMode);
-  REGISTER_OP(SETROUNDINGMODE, SetRoundingMode);
-  REGISTER_OP(INVALIDATEFLAGS,   NoOp);
-  REGISTER_OP(PROCESSORID,   ProcessorID);
-  REGISTER_OP(RDRAND, RDRAND);
-  REGISTER_OP(YIELD, Yield);
-
-#undef REGISTER_OP
-}
-}
-
@@ -1,79 +0,0 @@
-/*
-$info$
-tags: backend|arm64
-$end_info$
-*/
-
-#include "Interface/Core/JIT/Arm64/JITClass.h"
-
-namespace FEXCore::CPU {
-
-using namespace vixl;
-using namespace vixl::aarch64;
-#define DEF_OP(x) void Arm64JITCore::Op_##x(IR::IROp_Header *IROp, IR::NodeID Node)
-DEF_OP(ExtractElementPair) {
-  auto Op = IROp->C<IR::IROp_ExtractElementPair>();
-  switch (Op->Header.Size) {
-    case 4: {
-      auto Src = GetSrcPair<RA_32>(Op->Pair.ID());
-      std::array<aarch64::Register, 2> Regs = {Src.first, Src.second};
-      mov (GetReg<RA_32>(Node), Regs[Op->Element]);
-      break;
-    }
-    case 8: {
-      auto Src = GetSrcPair<RA_64>(Op->Pair.ID());
-      std::array<aarch64::Register, 2> Regs = {Src.first, Src.second};
-      mov (GetReg<RA_64>(Node), Regs[Op->Element]);
-      break;
-    }
-    default: LOGMAN_MSG_A_FMT("Unknown Size"); break;
-  }
-}
-
-DEF_OP(CreateElementPair) {
-  auto Op = IROp->C<IR::IROp_CreateElementPair>();
-  std::pair<aarch64::Register, aarch64::Register> Dst;
-  aarch64::Register RegFirst;
-  aarch64::Register RegSecond;
-  aarch64::Register RegTmp;
-
-  switch (IROp->ElementSize) {
-    case 4: {
-      Dst = GetSrcPair<RA_32>(Node);
-      RegFirst = GetReg<RA_32>(Op->Lower.ID());
-      RegSecond = GetReg<RA_32>(Op->Upper.ID());
-      RegTmp = w0;
-      break;
-    }
-    case 8: {
-      Dst = GetSrcPair<RA_64>(Node);
-      RegFirst = GetReg<RA_64>(Op->Lower.ID());
-      RegSecond = GetReg<RA_64>(Op->Upper.ID());
-      RegTmp = x0;
-      break;
-    }
-    default: LOGMAN_MSG_A_FMT("Unknown Size"); break;
-  }
-
-  if (Dst.first.GetCode() != RegSecond.GetCode()) {
-    mov(Dst.first, RegFirst);
-    mov(Dst.second, RegSecond);
-  } else if (Dst.second.GetCode() != RegFirst.GetCode()) {
-    mov(Dst.second, RegSecond);
-    mov(Dst.first, RegFirst);
-  } else {
-    mov(RegTmp, RegFirst);
-    mov(Dst.second, RegSecond);
-    mov(Dst.first, RegTmp);
-  }
-}
-
-#undef DEF_OP
-void Arm64JITCore::RegisterMoveHandlers() {
-#define REGISTER_OP(op, x) OpHandlers[FEXCore::IR::IROps::OP_##op] = &Arm64JITCore::Op_##x
-  REGISTER_OP(EXTRACTELEMENTPAIR, ExtractElementPair);
-  REGISTER_OP(CREATEELEMENTPAIR,  CreateElementPair);
-#undef REGISTER_OP
-}
-}
-
@@ -1,115 +0,0 @@
-#include <FEXCore/Core/SignalDelegator.h>
-#include <FEXCore/Utils/LogManager.h>
-#include <FEXHeaderUtils/Syscalls.h>
-
-#include <unistd.h>
-#include <signal.h>
-
-namespace FEXCore {
-  struct ThreadState {
-    FEXCore::Core::InternalThreadState *Thread{};
-  };
-
-  thread_local ThreadState ThreadData{};
-
-  static bool IsSynchronous(int Signal) {
-    switch (Signal) {
-    case SIGBUS:
-    case SIGFPE:
-    case SIGILL:
-    case SIGSEGV:
-    case SIGTRAP:
-      return true;
-    default: break;
-    };
-    return false;
-  }
-
-  /**
-   * @brief Masks signals from the signal mask
-   *
-   * @param how Argument to sigmask. SIG_{BLOCK, SETMASK, UNBLOCK}
-   * @param Signal Which signal to set or -1 to sweep through them all
-   */
-  static void MaskSignals(int how, int Signal = -1) {
-    // If we have a helper thread, we need to mask a significant amount of signals so the an errant thread doesn't receive a signal that it shouldn't
-    sigset_t SignalSet{};
-    sigemptyset(&SignalSet);
-
-    if (Signal == -1) {
-      for (int i = 0; i <= SignalDelegator::MAX_SIGNALS; ++i) {
-        // If it is a synchronous signal then don't ignore it
-        if (IsSynchronous(i)) {
-          continue;
-        }
-
-        // Add this signal to the ignore list
-        sigaddset(&SignalSet, i);
-      }
-    }
-    else {
-      sigaddset(&SignalSet, Signal);
-    }
-
-    // Be warned, a thread will inherit the signal mask if created from this thread
-    int Result = pthread_sigmask(how, &SignalSet, nullptr);
-    if (Result != 0) {
-      LogMan::Msg::EFmt("Couldn't register thread to mask signals");
-    }
-  }
-
-  void SignalDelegator::MaskThreadSignals() {
-    MaskSignals(SIG_BLOCK);
-  }
-
-  FEXCore::Core::InternalThreadState *SignalDelegator::GetTLSThread() {
-    return ThreadData.Thread;
-  }
-
-  void SignalDelegator::RegisterTLSState(FEXCore::Core::InternalThreadState *Thread) {
-    ThreadData.Thread = Thread;
-    RegisterFrontendTLSState(Thread);
-  }
-
-  void SignalDelegator::UninstallTLSState(FEXCore::Core::InternalThreadState *Thread) {
-    UninstallFrontendTLSState(Thread);
-    ThreadData.Thread = nullptr;
-  }
-
-  void SignalDelegator::RegisterHostSignalHandler(int Signal, HostSignalDelegatorFunction Func, bool Required) {
-    SetHostSignalHandler(Signal, Func, Required);
-    FrontendRegisterHostSignalHandler(Signal, Func, Required);
-  }
-
-  void SignalDelegator::RegisterFrontendHostSignalHandler(int Signal, HostSignalDelegatorFunction Func, bool Required) {
-    SetFrontendHostSignalHandler(Signal, Func, Required);
-    FrontendRegisterFrontendHostSignalHandler(Signal, Func, Required);
-  }
-
-  void SignalDelegator::HandleSignal(int Signal, void *Info, void *UContext) {
-    // Let the host take first stab at handling the signal
-    auto Thread = GetTLSThread();
-    HostSignalHandler &Handler = HostHandlers[Signal];
-
-    if (!Thread) {
-      LogMan::Msg::EFmt("[{}] Thread has received a signal and hasn't registered itself with the delegate! Programming error!", FHU::Syscalls::gettid());
-    }
-    else {
-      for (auto &Handler : Handler.Handlers) {
-        if (Handler(Thread, Signal, Info, UContext)) {
-          // If the host handler handled the fault then we can continue now
-          return;
-        }
-      }
-
-      if (Handler.FrontendHandler &&
-          Handler.FrontendHandler(Thread, Signal, Info, UContext)) {
-        return;
-      }
-
-      // Now let the frontend handle the signal
-      // It's clearly a guest signal and this ends up being an OS specific issue
-      HandleGuestSignal(Thread, Signal, Info, UContext);
-    }
-  }
-}
@@ -1,78 +0,0 @@
-/*
-$info$
-tags: glue|x86-guest-code
-desc: Guest-side assembly helpers used by the backends
-$end_info$
-*/
-
-#include "Interface/Core/X86HelperGen.h"
-
-#include <FEXCore/Config/Config.h>
-#include <FEXCore/Utils/Allocator.h>
-#include <FEXHeaderUtils/Syscalls.h>
-
-#include <cstdint>
-#include <cstring>
-#include <vector>
-#include <sys/mman.h>
-
-namespace FEXCore {
-constexpr size_t CODE_SIZE = 0x1000;
-
-X86GeneratedCode::X86GeneratedCode() {
-  // Allocate a page for our emulated guest
-  CodePtr = AllocateGuestCodeSpace(CODE_SIZE);
-
-  SignalReturn = reinterpret_cast<uint64_t>(CodePtr);
-  CallbackReturn = reinterpret_cast<uint64_t>(CodePtr) + 2;
-
-  const std::vector<uint8_t> SignalReturnCode = {
-    0x0F, 0x36, // SIGRET FEX instruction
-    0x0F, 0x37, // CALLBACKRET FEX Instruction
-  };
-
-  memcpy(CodePtr, &SignalReturnCode.at(0), SignalReturnCode.size());
-}
-
-X86GeneratedCode::~X86GeneratedCode() {
-  FEXCore::Allocator::munmap(CodePtr, CODE_SIZE);
-}
-
-void* X86GeneratedCode::AllocateGuestCodeSpace(size_t Size) {
-  FEX_CONFIG_OPT(Is64BitMode, IS64BIT_MODE);
-
-  if (Is64BitMode()) {
-    // 64bit mode can have its sigret handler anywhere
-    return FEXCore::Allocator::mmap(nullptr, Size, PROT_READ | PROT_WRITE, MAP_PRIVATE | MAP_ANONYMOUS, -1, 0);
-  }
-
-  // First 64bit page
-  constexpr uintptr_t LOCATION_MAX = 0x1'0000'0000;
-
-  // 32bit mode
-  // We need to have the sigret handler in the lower 32bits of memory space
-  // Scan top down and try to allocate a location
-  for (size_t Location = 0xFFFF'E000; Location != 0x0; Location -= 0x1000) {
-    void *Ptr = ::mmap(reinterpret_cast<void*>(Location), Size, PROT_READ | PROT_WRITE, MAP_FIXED_NOREPLACE | MAP_PRIVATE | MAP_ANONYMOUS, -1, 0);
-
-    if (Ptr != MAP_FAILED &&
-        reinterpret_cast<uintptr_t>(Ptr) >= LOCATION_MAX) {
-      // Failed to map in the lower 32bits
-      // Try again
-      // Can happen in the case that host kernel ignores MAP_FIXED_NOREPLACE
-      ::munmap(Ptr, Size);
-      continue;
-    }
-
-    if (Ptr != MAP_FAILED) {
-      return Ptr;
-    }
-  }
-
-  // Can't do anything about this
-  // Here's hoping the application doesn't use signals
-  return MAP_FAILED;
-}
-
-}
-
@@ -1,516 +0,0 @@
-/*
-$info$
-tags: frontend|x86-tables
-$end_info$
-*/
-
-#include "Interface/Core/X86Tables/X86Tables.h"
-
-#include <FEXCore/Debug/X86Tables.h>
-#include <iterator>
-
-namespace FEXCore::X86Tables {
-using namespace InstFlags;
-
-void InitializeVEXTables() {
-#define OPD(map_select, pp, opcode) (((map_select - 1) << 10) | (pp << 8) | (opcode))
-  static constexpr U16U8InfoStruct VEXTable[] = {
-    // Map 0 (Reserved)
-    // VEX Map 1
-    {OPD(1, 0b00, 0x10), 1, X86InstInfo{"VMOVUPS",   TYPE_UNDEC, FLAGS_NONE, 0, nullptr}},
-    {OPD(1, 0b01, 0x10), 1, X86InstInfo{"VMODUPD",   TYPE_UNDEC, FLAGS_NONE, 0, nullptr}},
-    {OPD(1, 0b10, 0x10), 1, X86InstInfo{"VMOVSS",    TYPE_UNDEC, FLAGS_NONE, 0, nullptr}},
-    {OPD(1, 0b11, 0x10), 1, X86InstInfo{"VMOVSD",    TYPE_UNDEC, FLAGS_NONE, 0, nullptr}},
-
-    {OPD(1, 0b00, 0x11), 1, X86InstInfo{"VMOVUPS",   TYPE_UNDEC, FLAGS_NONE, 0, nullptr}},
-    {OPD(1, 0b01, 0x11), 1, X86InstInfo{"VMODUPD",   TYPE_UNDEC, FLAGS_NONE, 0, nullptr}},
-    {OPD(1, 0b10, 0x11), 1, X86InstInfo{"VMOVSS",    TYPE_UNDEC, FLAGS_NONE, 0, nullptr}},
-    {OPD(1, 0b11, 0x11), 1, X86InstInfo{"VMOVSD",    TYPE_UNDEC, FLAGS_NONE, 0, nullptr}},
-
-    {OPD(1, 0b00, 0x12), 1, X86InstInfo{"VMOVLPS",   TYPE_UNDEC, FLAGS_NONE, 0, nullptr}},
-    {OPD(1, 0b01, 0x12), 1, X86InstInfo{"VMOVLPD",   TYPE_UNDEC, FLAGS_NONE, 0, nullptr}},
-    {OPD(1, 0b10, 0x12), 1, X86InstInfo{"VMOVSLDUP", TYPE_UNDEC, FLAGS_NONE, 0, nullptr}},
-    {OPD(1, 0b11, 0x12), 1, X86InstInfo{"VMOVDDUP",  TYPE_UNDEC, FLAGS_NONE, 0, nullptr}},
-
-    {OPD(1, 0b00, 0x13), 1, X86InstInfo{"VMOVLPS",   TYPE_UNDEC, FLAGS_NONE, 0, nullptr}},
-    {OPD(1, 0b01, 0x13), 1, X86InstInfo{"VMOVLPD",   TYPE_UNDEC, FLAGS_NONE, 0, nullptr}},
-
-    {OPD(1, 0b00, 0x14), 1, X86InstInfo{"VUNPCKLPS", TYPE_UNDEC, FLAGS_NONE, 0, nullptr}},
-    {OPD(1, 0b01, 0x14), 1, X86InstInfo{"VUNPCKLPD", TYPE_UNDEC, FLAGS_NONE, 0, nullptr}},
-
-    {OPD(1, 0b00, 0x15), 1, X86InstInfo{"VUNPCKHPS", TYPE_UNDEC, FLAGS_NONE, 0, nullptr}},
-    {OPD(1, 0b01, 0x15), 1, X86InstInfo{"VUNPCKHPD", TYPE_UNDEC, FLAGS_NONE, 0, nullptr}},
-
-    {OPD(1, 0b00, 0x16), 1, X86InstInfo{"VMOVHPS",   TYPE_UNDEC, FLAGS_NONE, 0, nullptr}},
-    {OPD(1, 0b01, 0x16), 1, X86InstInfo{"VMOVHPD",   TYPE_UNDEC, FLAGS_NONE, 0, nullptr}},
-    {OPD(1, 0b10, 0x16), 1, X86InstInfo{"VMOVSHDUP", TYPE_UNDEC, FLAGS_NONE, 0, nullptr}},
-
-    {OPD(1, 0b00, 0x17), 1, X86InstInfo{"VMOVHPS",   TYPE_UNDEC, FLAGS_NONE, 0, nullptr}},
-    {OPD(1, 0b01, 0x17), 1, X86InstInfo{"VMOVHPD",   TYPE_UNDEC, FLAGS_NONE, 0, nullptr}},
-
-    {OPD(1, 0b00, 0x50), 1, X86InstInfo{"VMOVMSKPS", TYPE_UNDEC, FLAGS_NONE, 0, nullptr}},
-    {OPD(1, 0b01, 0x50), 1, X86InstInfo{"VMOVMSKPD", TYPE_UNDEC, FLAGS_NONE, 0, nullptr}},
-
-    {OPD(1, 0b00, 0x51), 1, X86InstInfo{"VSQRTPS",   TYPE_UNDEC, FLAGS_NONE, 0, nullptr}},
-    {OPD(1, 0b01, 0x51), 1, X86InstInfo{"VSQRTPD",   TYPE_UNDEC, FLAGS_NONE, 0, nullptr}},
-    {OPD(1, 0b10, 0x51), 1, X86InstInfo{"VSQRTSS",   TYPE_UNDEC, FLAGS_NONE, 0, nullptr}},
-    {OPD(1, 0b11, 0x51), 1, X86InstInfo{"VSQRTSD",   TYPE_UNDEC, FLAGS_NONE, 0, nullptr}},
-
-    {OPD(1, 0b00, 0x52), 1, X86InstInfo{"VRSQRTPS",  TYPE_UNDEC, FLAGS_NONE, 0, nullptr}},
-    {OPD(1, 0b10, 0x52), 1, X86InstInfo{"VRSQRTSS",  TYPE_UNDEC, FLAGS_NONE, 0, nullptr}},
-
-    {OPD(1, 0b00, 0x53), 1, X86InstInfo{"VRCPPS",    TYPE_UNDEC, FLAGS_NONE, 0, nullptr}},
-    {OPD(1, 0b10, 0x53), 1, X86InstInfo{"VRCPSS",    TYPE_UNDEC, FLAGS_NONE, 0, nullptr}},
-
-    {OPD(1, 0b00, 0x54), 1, X86InstInfo{"VANDPS",   TYPE_UNDEC, FLAGS_NONE, 0, nullptr}},
-    {OPD(1, 0b01, 0x54), 1, X86InstInfo{"VANDPD",   TYPE_UNDEC, FLAGS_NONE, 0, nullptr}},
-
-    {OPD(1, 0b00, 0x55), 1, X86InstInfo{"VANDNPS",   TYPE_UNDEC, FLAGS_NONE, 0, nullptr}},
-    {OPD(1, 0b01, 0x55), 1, X86InstInfo{"VANDNPD",   TYPE_UNDEC, FLAGS_NONE, 0, nullptr}},
-
-    {OPD(1, 0b00, 0x56), 1, X86InstInfo{"VORPS",   TYPE_UNDEC, FLAGS_NONE, 0, nullptr}},
-    {OPD(1, 0b01, 0x56), 1, X86InstInfo{"VORPD",   TYPE_UNDEC, FLAGS_NONE, 0, nullptr}},
-
-    {OPD(1, 0b00, 0x57), 1, X86InstInfo{"VXORPS",   TYPE_UNDEC, FLAGS_NONE, 0, nullptr}},
-    {OPD(1, 0b01, 0x57), 1, X86InstInfo{"VDORPD",   TYPE_UNDEC, FLAGS_NONE, 0, nullptr}},
-
-    {OPD(1, 0b01, 0x60), 1, X86InstInfo{"VPUNPCKLBW", TYPE_UNDEC, FLAGS_NONE, 0, nullptr}},
-    {OPD(1, 0b01, 0x61), 1, X86InstInfo{"VPUNPCKLWD", TYPE_UNDEC, FLAGS_NONE, 0, nullptr}},
-    {OPD(1, 0b01, 0x62), 1, X86InstInfo{"VPUNPCKLDQ", TYPE_UNDEC, FLAGS_NONE, 0, nullptr}},
-    {OPD(1, 0b01, 0x63), 1, X86InstInfo{"VPACKSSWB",  TYPE_UNDEC, FLAGS_NONE, 0, nullptr}},
-    {OPD(1, 0b01, 0x64), 1, X86InstInfo{"VPCMPGTB",   TYPE_INST, FLAGS_MODRM | FLAGS_XMM_FLAGS, 0, nullptr}},
-    {OPD(1, 0b01, 0x65), 1, X86InstInfo{"VPVMPGTW",   TYPE_INST, FLAGS_MODRM | FLAGS_XMM_FLAGS, 0, nullptr}},
-    {OPD(1, 0b01, 0x66), 1, X86InstInfo{"VPVMPGTD",   TYPE_INST, FLAGS_MODRM | FLAGS_XMM_FLAGS, 0, nullptr}},
-    {OPD(1, 0b01, 0x67), 1, X86InstInfo{"VPACKUSWB",  TYPE_UNDEC, FLAGS_NONE, 0, nullptr}},
-
-    {OPD(1, 0b01, 0x70), 1, X86InstInfo{"VPSHUFD",    TYPE_UNDEC, FLAGS_NONE, 0, nullptr}},
-    {OPD(1, 0b10, 0x70), 1, X86InstInfo{"VPSHUFHW",   TYPE_UNDEC, FLAGS_NONE, 0, nullptr}},
-    {OPD(1, 0b11, 0x70), 1, X86InstInfo{"VPSHUFLW",   TYPE_UNDEC, FLAGS_NONE, 0, nullptr}},
-
-    {OPD(1, 0b01, 0x71), 1, X86InstInfo{"",           TYPE_VEX_GROUP_12, FLAGS_NONE, 0, nullptr}}, // VEX Group 12
-    {OPD(1, 0b01, 0x72), 1, X86InstInfo{"",           TYPE_VEX_GROUP_13, FLAGS_NONE, 0, nullptr}}, // VEX Group 13
-    {OPD(1, 0b01, 0x73), 1, X86InstInfo{"",           TYPE_VEX_GROUP_14, FLAGS_NONE, 0, nullptr}}, // VEX Group 14
-
-    {OPD(1, 0b01, 0x74), 1, X86InstInfo{"VPCMPEQB",   TYPE_INST, FLAGS_MODRM | FLAGS_XMM_FLAGS, 0, nullptr}},
-    {OPD(1, 0b01, 0x75), 1, X86InstInfo{"VPCMPEQW",   TYPE_INST, FLAGS_MODRM | FLAGS_XMM_FLAGS, 0, nullptr}},
-    {OPD(1, 0b01, 0x76), 1, X86InstInfo{"VPCMPEQD",   TYPE_INST, FLAGS_MODRM | FLAGS_XMM_FLAGS, 0, nullptr}},
-
-    {OPD(1, 0b00, 0x77), 1, X86InstInfo{"VZERO*",     TYPE_INST, FLAGS_NONE, 0, nullptr}},
-
-    {OPD(1, 0b00, 0xC2), 1, X86InstInfo{"VCMPccPS",   TYPE_UNDEC, FLAGS_NONE, 0, nullptr}},
-    {OPD(1, 0b01, 0xC2), 1, X86InstInfo{"VCMPccPD",   TYPE_UNDEC, FLAGS_NONE, 0, nullptr}},
-    {OPD(1, 0b10, 0xC2), 1, X86InstInfo{"VCMPccSS",   TYPE_UNDEC, FLAGS_NONE, 0, nullptr}},
-    {OPD(1, 0b11, 0xC2), 1, X86InstInfo{"VCMPccSD",   TYPE_UNDEC, FLAGS_NONE, 0, nullptr}},
-
-    {OPD(1, 0b01, 0xC4), 1, X86InstInfo{"VPINSRW",    TYPE_UNDEC, FLAGS_NONE, 0, nullptr}},
-    {OPD(1, 0b01, 0xC5), 1, X86InstInfo{"VPEXTRW",    TYPE_UNDEC, FLAGS_NONE, 0, nullptr}},
-
-    {OPD(1, 0b00, 0xC6), 1, X86InstInfo{"VSHUFPS",    TYPE_UNDEC, FLAGS_NONE, 0, nullptr}},
-    {OPD(1, 0b01, 0xC6), 1, X86InstInfo{"VSHUFPD",    TYPE_UNDEC, FLAGS_NONE, 0, nullptr}},
-
-    // The above ops are defined from `Table A-17. VEX Opcode Map 1, Low Nibble = [0h:7h]` of AMD Architecture programmer's manual Volume 3
-    // This table doesn't state which VEX.pp is for which instruction
-    // XXX: Confirm all the above encoding opcodes
-
-    {OPD(1, 0b00, 0x28), 1, X86InstInfo{"VMOVAPS",   TYPE_UNDEC, FLAGS_NONE, 0, nullptr}},
-    {OPD(1, 0b01, 0x28), 1, X86InstInfo{"VMOVAPD",   TYPE_UNDEC, FLAGS_NONE, 0, nullptr}},
-
-    {OPD(1, 0b00, 0x29), 1, X86InstInfo{"VMOVAPS",   TYPE_UNDEC, FLAGS_NONE, 0, nullptr}},
-    {OPD(1, 0b01, 0x29), 1, X86InstInfo{"VMOVAPD",   TYPE_UNDEC, FLAGS_NONE, 0, nullptr}},
-
-    {OPD(1, 0b10, 0x2A), 1, X86InstInfo{"VCVTSI2SS",   TYPE_UNDEC, FLAGS_NONE, 0, nullptr}},
-    {OPD(1, 0b11, 0x2A), 1, X86InstInfo{"VCVTSI2SD",   TYPE_UNDEC, FLAGS_NONE, 0, nullptr}},
-
-    {OPD(1, 0b00, 0x2B), 1, X86InstInfo{"VMOVNTPS",   TYPE_UNDEC, FLAGS_NONE, 0, nullptr}},
-    {OPD(1, 0b01, 0x2B), 1, X86InstInfo{"VMOVNTPD",   TYPE_UNDEC, FLAGS_NONE, 0, nullptr}},
-
-    {OPD(1, 0b10, 0x2C), 1, X86InstInfo{"VCVTTSS2SI",   TYPE_UNDEC, FLAGS_NONE, 0, nullptr}},
-    {OPD(1, 0b11, 0x2C), 1, X86InstInfo{"VCVTTSD2SI",   TYPE_UNDEC, FLAGS_NONE, 0, nullptr}},
-
-    {OPD(1, 0b10, 0x2D), 1, X86InstInfo{"VCVTSS2SI",   TYPE_UNDEC, FLAGS_NONE, 0, nullptr}},
-    {OPD(1, 0b11, 0x2D), 1, X86InstInfo{"VCVTSD2SI",   TYPE_UNDEC, FLAGS_NONE, 0, nullptr}},
-
-    {OPD(1, 0b00, 0x2E), 1, X86InstInfo{"VUCOMISS",   TYPE_UNDEC, FLAGS_NONE, 0, nullptr}},
-    {OPD(1, 0b01, 0x2E), 1, X86InstInfo{"VUCOMISD",   TYPE_UNDEC, FLAGS_NONE, 0, nullptr}},
-
-    {OPD(1, 0b00, 0x2F), 1, X86InstInfo{"VUCOMISS",   TYPE_UNDEC, FLAGS_NONE, 0, nullptr}},
-    {OPD(1, 0b01, 0x2F), 1, X86InstInfo{"VUCOMISD",   TYPE_UNDEC, FLAGS_NONE, 0, nullptr}},
-
-    {OPD(1, 0b00, 0x58), 1, X86InstInfo{"VADDPS",   TYPE_UNDEC, FLAGS_NONE, 0, nullptr}},
-    {OPD(1, 0b01, 0x58), 1, X86InstInfo{"VADDPD",   TYPE_UNDEC, FLAGS_NONE, 0, nullptr}},
-    {OPD(1, 0b10, 0x58), 1, X86InstInfo{"VADDSS",   TYPE_UNDEC, FLAGS_NONE, 0, nullptr}},
-    {OPD(1, 0b11, 0x58), 1, X86InstInfo{"VADDSD",   TYPE_UNDEC, FLAGS_NONE, 0, nullptr}},
-
-    {OPD(1, 0b00, 0x59), 1, X86InstInfo{"VMULPS",   TYPE_UNDEC, FLAGS_NONE, 0, nullptr}},
-    {OPD(1, 0b01, 0x59), 1, X86InstInfo{"VMULPD",   TYPE_UNDEC, FLAGS_NONE, 0, nullptr}},
-    {OPD(1, 0b10, 0x59), 1, X86InstInfo{"VMULSS",   TYPE_UNDEC, FLAGS_NONE, 0, nullptr}},
-    {OPD(1, 0b11, 0x59), 1, X86InstInfo{"VMULSD",   TYPE_UNDEC, FLAGS_NONE, 0, nullptr}},
-
-    {OPD(1, 0b00, 0x5B), 1, X86InstInfo{"VCVTDQ2PS",   TYPE_UNDEC, FLAGS_NONE, 0, nullptr}},
-    {OPD(1, 0b01, 0x5B), 1, X86InstInfo{"VCVTPS2DQ",   TYPE_UNDEC, FLAGS_NONE, 0, nullptr}},
-    {OPD(1, 0b10, 0x5B), 1, X86InstInfo{"VCVTPS2DQ",   TYPE_UNDEC, FLAGS_NONE, 0, nullptr}},
-
-    {OPD(1, 0b00, 0x5C), 1, X86InstInfo{"VSUBPS",   TYPE_UNDEC, FLAGS_NONE, 0, nullptr}},
-    {OPD(1, 0b01, 0x5C), 1, X86InstInfo{"VSUBPD",   TYPE_UNDEC, FLAGS_NONE, 0, nullptr}},
-    {OPD(1, 0b10, 0x5C), 1, X86InstInfo{"VSUBSS",   TYPE_UNDEC, FLAGS_NONE, 0, nullptr}},
-    {OPD(1, 0b11, 0x5C), 1, X86InstInfo{"VSUBSD",   TYPE_UNDEC, FLAGS_NONE, 0, nullptr}},
-
-    {OPD(1, 0b00, 0x5D), 1, X86InstInfo{"VMINPS",   TYPE_UNDEC, FLAGS_NONE, 0, nullptr}},
-    {OPD(1, 0b01, 0x5D), 1, X86InstInfo{"VMINPD",   TYPE_UNDEC, FLAGS_NONE, 0, nullptr}},
-    {OPD(1, 0b10, 0x5D), 1, X86InstInfo{"VMINSS",   TYPE_UNDEC, FLAGS_NONE, 0, nullptr}},
-    {OPD(1, 0b11, 0x5D), 1, X86InstInfo{"VMINSD",   TYPE_UNDEC, FLAGS_NONE, 0, nullptr}},
-
-    {OPD(1, 0b00, 0x5E), 1, X86InstInfo{"VDIVPS",   TYPE_UNDEC, FLAGS_NONE, 0, nullptr}},
-    {OPD(1, 0b01, 0x5E), 1, X86InstInfo{"VDIVPD",   TYPE_UNDEC, FLAGS_NONE, 0, nullptr}},
-    {OPD(1, 0b10, 0x5E), 1, X86InstInfo{"VDIVSS",   TYPE_UNDEC, FLAGS_NONE, 0, nullptr}},
-    {OPD(1, 0b11, 0x5E), 1, X86InstInfo{"VDIVSD",   TYPE_UNDEC, FLAGS_NONE, 0, nullptr}},
-
-    {OPD(1, 0b00, 0x5F), 1, X86InstInfo{"VMAXPS",   TYPE_UNDEC, FLAGS_NONE, 0, nullptr}},
-    {OPD(1, 0b01, 0x5F), 1, X86InstInfo{"VMAXPD",   TYPE_UNDEC, FLAGS_NONE, 0, nullptr}},
-    {OPD(1, 0b10, 0x5F), 1, X86InstInfo{"VMAXSS",   TYPE_UNDEC, FLAGS_NONE, 0, nullptr}},
-    {OPD(1, 0b11, 0x5F), 1, X86InstInfo{"VMAXSD",   TYPE_UNDEC, FLAGS_NONE, 0, nullptr}},
-
-
-    {OPD(1, 0b01, 0x68), 1, X86InstInfo{"VPUNPCKHBW",  TYPE_UNDEC, FLAGS_NONE, 0, nullptr}},
-    {OPD(1, 0b01, 0x69), 1, X86InstInfo{"VPUNPCKHWD",  TYPE_UNDEC, FLAGS_NONE, 0, nullptr}},
-    {OPD(1, 0b01, 0x6A), 1, X86InstInfo{"VPUNPCKHDQ",  TYPE_UNDEC, FLAGS_NONE, 0, nullptr}},
-    {OPD(1, 0b01, 0x6B), 1, X86InstInfo{"VPACKSSDW",   TYPE_UNDEC, FLAGS_NONE, 0, nullptr}},
-    {OPD(1, 0b01, 0x6C), 1, X86InstInfo{"VPUNPCKLQDQ", TYPE_UNDEC, FLAGS_NONE, 0, nullptr}},
-    {OPD(1, 0b01, 0x6D), 1, X86InstInfo{"VPUNPCKHQDQ", TYPE_UNDEC, FLAGS_NONE, 0, nullptr}},
-    {OPD(1, 0b01, 0x6E), 1, X86InstInfo{"VMOV*",       TYPE_INST, GenFlagsDstSize(SIZE_128BIT) | FLAGS_MODRM | FLAGS_XMM_FLAGS | FLAGS_SF_SRC_GPR, 0, nullptr}},
-
-    {OPD(1, 0b01, 0x6F), 1, X86InstInfo{"VMOVDQA",     TYPE_INST, FLAGS_MODRM | FLAGS_XMM_FLAGS, 0, nullptr}},
-    {OPD(1, 0b10, 0x6F), 1, X86InstInfo{"VMOVDQU",     TYPE_INST, FLAGS_MODRM | FLAGS_XMM_FLAGS, 0, nullptr}},
-
-    {OPD(1, 0b01, 0x7C), 1, X86InstInfo{"VHADDPD",     TYPE_UNDEC, FLAGS_NONE, 0, nullptr}},
-    {OPD(1, 0b11, 0x7C), 1, X86InstInfo{"VHADDPS",     TYPE_UNDEC, FLAGS_NONE, 0, nullptr}},
-
-    {OPD(1, 0b01, 0x7D), 1, X86InstInfo{"VHSUBPD",     TYPE_UNDEC, FLAGS_NONE, 0, nullptr}},
-    {OPD(1, 0b11, 0x7D), 1, X86InstInfo{"VHSUBPS",     TYPE_UNDEC, FLAGS_NONE, 0, nullptr}},
-
-    {OPD(1, 0b01, 0x7E), 1, X86InstInfo{"VMOV*",     TYPE_INST, FLAGS_MODRM | FLAGS_XMM_FLAGS, 0, nullptr}},
-    {OPD(1, 0b10, 0x7E), 1, X86InstInfo{"VMOVQ",     TYPE_INST, FLAGS_MODRM | FLAGS_XMM_FLAGS, 0, nullptr}},
-
-    {OPD(1, 0b01, 0x7F), 1, X86InstInfo{"VMOVDQA",     TYPE_INST, FLAGS_MODRM | FLAGS_SF_MOD_DST | FLAGS_XMM_FLAGS, 0, nullptr}},
-    {OPD(1, 0b10, 0x7F), 1, X86InstInfo{"VMOVDQU",     TYPE_INST, FLAGS_MODRM | FLAGS_SF_MOD_DST | FLAGS_XMM_FLAGS, 0, nullptr}},
-
-    {OPD(1, 0b00, 0xAE), 1, X86InstInfo{"",     TYPE_VEX_GROUP_15, FLAGS_NONE, 0, nullptr}}, // VEX Group 15
-    {OPD(1, 0b01, 0xAE), 1, X86InstInfo{"",     TYPE_VEX_GROUP_15, FLAGS_NONE, 0, nullptr}}, // VEX Group 15
-    {OPD(1, 0b10, 0xAE), 1, X86InstInfo{"",     TYPE_VEX_GROUP_15, FLAGS_NONE, 0, nullptr}}, // VEX Group 15
-    {OPD(1, 0b11, 0xAE), 1, X86InstInfo{"",     TYPE_VEX_GROUP_15, FLAGS_NONE, 0, nullptr}}, // VEX Group 15
-
-    {OPD(1, 0b01, 0xD0), 1, X86InstInfo{"VADDSUBPD",   TYPE_UNDEC, FLAGS_NONE, 0, nullptr}},
-    {OPD(1, 0b11, 0xD0), 1, X86InstInfo{"VADDSUBPS",   TYPE_UNDEC, FLAGS_NONE, 0, nullptr}},
-
-    {OPD(1, 0b01, 0xD1), 1, X86InstInfo{"VPSRLW",      TYPE_UNDEC, FLAGS_NONE, 0, nullptr}},
-    {OPD(1, 0b01, 0xD2), 1, X86InstInfo{"VPSRLD",      TYPE_UNDEC, FLAGS_NONE, 0, nullptr}},
-    {OPD(1, 0b01, 0xD3), 1, X86InstInfo{"VPSRLQ",      TYPE_UNDEC, FLAGS_NONE, 0, nullptr}},
-    {OPD(1, 0b01, 0xD4), 1, X86InstInfo{"VPADDQ",      TYPE_INST, GenFlagsSameSize(SIZE_256BIT) | FLAGS_MODRM | FLAGS_XMM_FLAGS, 0, nullptr}},
-    {OPD(1, 0b01, 0xD5), 1, X86InstInfo{"VPMULLW",     TYPE_UNDEC, FLAGS_NONE, 0, nullptr}},
-    {OPD(1, 0b01, 0xD6), 1, X86InstInfo{"VMOVQ",       TYPE_INST, FLAGS_MODRM | FLAGS_SF_MOD_DST | FLAGS_XMM_FLAGS, 0, nullptr}},
-    {OPD(1, 0b01, 0xD7), 1, X86InstInfo{"VPMOVMSKB",   TYPE_INST, FLAGS_MODRM | FLAGS_XMM_FLAGS | FLAGS_SF_DST_GPR | FLAGS_SF_MOD_REG_ONLY, 0, nullptr}},
-
-    {OPD(1, 0b01, 0xD8), 1, X86InstInfo{"VPSUBUSB", TYPE_INST, FLAGS_MODRM | FLAGS_XMM_FLAGS, 0, nullptr}},
-    {OPD(1, 0b01, 0xD9), 1, X86InstInfo{"VPSUBUSW", TYPE_INST, FLAGS_MODRM | FLAGS_XMM_FLAGS, 0, nullptr}},
-    {OPD(1, 0b01, 0xDA), 1, X86InstInfo{"VPMINUB",  TYPE_INST, FLAGS_MODRM | FLAGS_XMM_FLAGS, 0, nullptr}},
-    {OPD(1, 0b01, 0xDB), 1, X86InstInfo{"VPAND",    TYPE_INST, FLAGS_MODRM | FLAGS_XMM_FLAGS, 0, nullptr}},
-    {OPD(1, 0b01, 0xDC), 1, X86InstInfo{"VPADDUSB", TYPE_INST, FLAGS_MODRM | FLAGS_XMM_FLAGS, 0, nullptr}},
-    {OPD(1, 0b01, 0xDD), 1, X86InstInfo{"VPADDUSW", TYPE_INST, FLAGS_MODRM | FLAGS_XMM_FLAGS, 0, nullptr}},
-    {OPD(1, 0b01, 0xDE), 1, X86InstInfo{"VPMAXUB",  TYPE_INST, FLAGS_MODRM | FLAGS_XMM_FLAGS, 0, nullptr}},
-    {OPD(1, 0b01, 0xDF), 1, X86InstInfo{"VPANDN",   TYPE_INST, FLAGS_MODRM | FLAGS_XMM_FLAGS, 0, nullptr}},
-
-    {OPD(1, 0b01, 0xE0), 1, X86InstInfo{"VPAVGB",      TYPE_UNDEC, FLAGS_NONE, 0, nullptr}},
-    {OPD(1, 0b01, 0xE1), 1, X86InstInfo{"VPSRAW",      TYPE_UNDEC, FLAGS_NONE, 0, nullptr}},
-    {OPD(1, 0b01, 0xE2), 1, X86InstInfo{"VPSRAD",      TYPE_UNDEC, FLAGS_NONE, 0, nullptr}},
-    {OPD(1, 0b01, 0xE3), 1, X86InstInfo{"VPAVGW",      TYPE_UNDEC, FLAGS_NONE, 0, nullptr}},
-    {OPD(1, 0b01, 0xE4), 1, X86InstInfo{"VPMULHUW",    TYPE_UNDEC, FLAGS_NONE, 0, nullptr}},
-    {OPD(1, 0b01, 0xE5), 1, X86InstInfo{"VPMULHW",     TYPE_UNDEC, FLAGS_NONE, 0, nullptr}},
-
-    {OPD(1, 0b01, 0xE6), 1, X86InstInfo{"VCVTTPD2DQ",  TYPE_UNDEC, FLAGS_NONE, 0, nullptr}},
-    {OPD(1, 0b10, 0xE6), 1, X86InstInfo{"VCVTDQ2PD",   TYPE_UNDEC, FLAGS_NONE, 0, nullptr}},
-    {OPD(1, 0b11, 0xE6), 1, X86InstInfo{"VCVTPD2DQ",   TYPE_UNDEC, FLAGS_NONE, 0, nullptr}},
-
-    {OPD(1, 0b01, 0xE7), 1, X86InstInfo{"VMOVNTDQ",    TYPE_INST, FLAGS_MODRM | FLAGS_SF_MOD_DST | FLAGS_XMM_FLAGS, 0, nullptr}},
-
-    {OPD(1, 0b01, 0xE8), 1, X86InstInfo{"VPSUBSB", TYPE_UNDEC, FLAGS_NONE, 0, nullptr}},
-    {OPD(1, 0b01, 0xE9), 1, X86InstInfo{"VPSUBSW", TYPE_UNDEC, FLAGS_NONE, 0, nullptr}},
-    {OPD(1, 0b01, 0xEA), 1, X86InstInfo{"VPMINSW",  TYPE_UNDEC, FLAGS_NONE, 0, nullptr}},
-    {OPD(1, 0b01, 0xEB), 1, X86InstInfo{"VPOR",    TYPE_INST, FLAGS_MODRM | FLAGS_XMM_FLAGS, 0, nullptr}},
-    {OPD(1, 0b01, 0xEC), 1, X86InstInfo{"VPADDSB", TYPE_UNDEC, FLAGS_NONE, 0, nullptr}},
-    {OPD(1, 0b01, 0xED), 1, X86InstInfo{"VPADDSW", TYPE_UNDEC, FLAGS_NONE, 0, nullptr}},
-    {OPD(1, 0b01, 0xEE), 1, X86InstInfo{"VPMAXSW",  TYPE_UNDEC, FLAGS_NONE, 0, nullptr}},
-    {OPD(1, 0b01, 0xEF), 1, X86InstInfo{"VPXOR",   TYPE_INST, FLAGS_MODRM | FLAGS_XMM_FLAGS, 0, nullptr}},
-
-    {OPD(1, 0b11, 0xF0), 1, X86InstInfo{"VLDDQU",      TYPE_UNDEC, FLAGS_NONE, 0, nullptr}},
-
-    {OPD(1, 0b01, 0xF1), 1, X86InstInfo{"VPSLLW",      TYPE_UNDEC, FLAGS_NONE, 0, nullptr}},
-    {OPD(1, 0b01, 0xF2), 1, X86InstInfo{"VPSLLD",      TYPE_UNDEC, FLAGS_NONE, 0, nullptr}},
-    {OPD(1, 0b01, 0xF3), 1, X86InstInfo{"VPSLLQ",      TYPE_UNDEC, FLAGS_NONE, 0, nullptr}},
-    {OPD(1, 0b01, 0xF4), 1, X86InstInfo{"VPMULUDQ",    TYPE_UNDEC, FLAGS_NONE, 0, nullptr}},
-    {OPD(1, 0b01, 0xF5), 1, X86InstInfo{"VPMADDWD",    TYPE_UNDEC, FLAGS_NONE, 0, nullptr}},
-    {OPD(1, 0b01, 0xF6), 1, X86InstInfo{"VPSADBW",     TYPE_UNDEC, FLAGS_NONE, 0, nullptr}},
-    {OPD(1, 0b01, 0xF7), 1, X86InstInfo{"VMASKMOVDQU", TYPE_UNDEC, FLAGS_NONE, 0, nullptr}},
-
-    {OPD(1, 0b01, 0xF8), 1, X86InstInfo{"VPSUBB", TYPE_INST, GenFlagsSameSize(SIZE_256BIT) | FLAGS_MODRM | FLAGS_XMM_FLAGS, 0, nullptr}},
-    {OPD(1, 0b01, 0xF9), 1, X86InstInfo{"VPSUBW", TYPE_INST, GenFlagsSameSize(SIZE_256BIT) | FLAGS_MODRM | FLAGS_XMM_FLAGS, 0, nullptr}},
-    {OPD(1, 0b01, 0xFA), 1, X86InstInfo{"VPSUBD", TYPE_INST, GenFlagsSameSize(SIZE_256BIT) | FLAGS_MODRM | FLAGS_XMM_FLAGS, 0, nullptr}},
-    {OPD(1, 0b01, 0xFB), 1, X86InstInfo{"VPSUBQ", TYPE_INST, GenFlagsSameSize(SIZE_256BIT) | FLAGS_MODRM | FLAGS_XMM_FLAGS, 0, nullptr}},
-    {OPD(1, 0b01, 0xFC), 1, X86InstInfo{"VPADDB", TYPE_INST, GenFlagsSameSize(SIZE_256BIT) | FLAGS_MODRM | FLAGS_XMM_FLAGS, 0, nullptr}},
-    {OPD(1, 0b01, 0xFD), 1, X86InstInfo{"VPADDW", TYPE_INST, GenFlagsSameSize(SIZE_256BIT) | FLAGS_MODRM | FLAGS_XMM_FLAGS, 0, nullptr}},
-    {OPD(1, 0b01, 0xFE), 1, X86InstInfo{"VPADDD", TYPE_INST, GenFlagsSameSize(SIZE_256BIT) | FLAGS_MODRM | FLAGS_XMM_FLAGS, 0, nullptr}},
-
-    // VEX Map 2
-    {OPD(2, 0b01, 0x00), 1, X86InstInfo{"VPSHUFB", TYPE_INST, FLAGS_MODRM | FLAGS_XMM_FLAGS, 0, nullptr}},
-    {OPD(2, 0b01, 0x01), 1, X86InstInfo{"VPADDW", TYPE_UNDEC, FLAGS_NONE, 0, nullptr}},
-    {OPD(2, 0b01, 0x02), 1, X86InstInfo{"VPHADDD", TYPE_UNDEC, FLAGS_NONE, 0, nullptr}},
-    {OPD(2, 0b01, 0x03), 1, X86InstInfo{"VPHADDSW", TYPE_UNDEC, FLAGS_NONE, 0, nullptr}},
-    {OPD(2, 0b01, 0x04), 1, X86InstInfo{"VPMADDUBSW", TYPE_UNDEC, FLAGS_NONE, 0, nullptr}},
-    {OPD(2, 0b01, 0x05), 1, X86InstInfo{"VPHSUBW", TYPE_UNDEC, FLAGS_NONE, 0, nullptr}},
-    {OPD(2, 0b01, 0x06), 1, X86InstInfo{"VPHSUBD", TYPE_UNDEC, FLAGS_NONE, 0, nullptr}},
-    {OPD(2, 0b01, 0x07), 1, X86InstInfo{"VPHSUBSW", TYPE_UNDEC, FLAGS_NONE, 0, nullptr}},
-
-    {OPD(2, 0b01, 0x08), 1, X86InstInfo{"VPSIGNB", TYPE_UNDEC, FLAGS_NONE, 0, nullptr}},
-    {OPD(2, 0b01, 0x09), 1, X86InstInfo{"VPSIGNW", TYPE_UNDEC, FLAGS_NONE, 0, nullptr}},
-    {OPD(2, 0b01, 0x0A), 1, X86InstInfo{"VPSIGND", TYPE_UNDEC, FLAGS_NONE, 0, nullptr}},
-    {OPD(2, 0b01, 0x0B), 1, X86InstInfo{"VPMULHRSW", TYPE_UNDEC, FLAGS_NONE, 0, nullptr}},
-    {OPD(2, 0b01, 0x0C), 1, X86InstInfo{"VPERMILPS", TYPE_UNDEC, FLAGS_NONE, 0, nullptr}},
-    {OPD(2, 0b01, 0x0D), 1, X86InstInfo{"VPERMILPD", TYPE_UNDEC, FLAGS_NONE, 0, nullptr}},
-    {OPD(2, 0b01, 0x0E), 1, X86InstInfo{"VTESTPS", TYPE_UNDEC, FLAGS_NONE, 0, nullptr}},
-    {OPD(2, 0b01, 0x0F), 1, X86InstInfo{"VTESTPD", TYPE_UNDEC, FLAGS_NONE, 0, nullptr}},
-
-    {OPD(2, 0b01, 0x13), 1, X86InstInfo{"VCVTPH2PS", TYPE_UNDEC, FLAGS_NONE, 0, nullptr}},
-    {OPD(2, 0b01, 0x16), 1, X86InstInfo{"VPERMPS", TYPE_UNDEC, FLAGS_NONE, 0, nullptr}},
-    {OPD(2, 0b01, 0x17), 1, X86InstInfo{"VPTEST", TYPE_UNDEC, FLAGS_NONE, 0, nullptr}},
-
-    {OPD(2, 0b01, 0x18), 1, X86InstInfo{"VBROADCASTSS", TYPE_UNDEC, FLAGS_NONE, 0, nullptr}},
-    {OPD(2, 0b01, 0x19), 1, X86InstInfo{"VBROADCASTSD", TYPE_UNDEC, FLAGS_NONE, 0, nullptr}},
-    {OPD(2, 0b01, 0x1A), 1, X86InstInfo{"VBROADCASTF128", TYPE_UNDEC, FLAGS_NONE, 0, nullptr}},
-    {OPD(2, 0b01, 0x1C), 1, X86InstInfo{"VPABSB", TYPE_UNDEC, FLAGS_NONE, 0, nullptr}},
-    {OPD(2, 0b01, 0x1D), 1, X86InstInfo{"VPABSW", TYPE_UNDEC, FLAGS_NONE, 0, nullptr}},
-    {OPD(2, 0b01, 0x1E), 1, X86InstInfo{"VPABSD", TYPE_UNDEC, FLAGS_NONE, 0, nullptr}},
-
-    {OPD(2, 0b01, 0x20), 1, X86InstInfo{"VPMOVSXBW", TYPE_UNDEC, FLAGS_NONE, 0, nullptr}},
-    {OPD(2, 0b01, 0x21), 1, X86InstInfo{"VPMOVSXBD", TYPE_UNDEC, FLAGS_NONE, 0, nullptr}},
-    {OPD(2, 0b01, 0x22), 1, X86InstInfo{"VPMOVSXBQ", TYPE_UNDEC, FLAGS_NONE, 0, nullptr}},
-    {OPD(2, 0b01, 0x23), 1, X86InstInfo{"VPMOVSXWD", TYPE_UNDEC, FLAGS_NONE, 0, nullptr}},
-    {OPD(2, 0b01, 0x24), 1, X86InstInfo{"VPMOVSXWQ", TYPE_UNDEC, FLAGS_NONE, 0, nullptr}},
-    {OPD(2, 0b01, 0x25), 1, X86InstInfo{"VPMOVSXDQ", TYPE_UNDEC, FLAGS_NONE, 0, nullptr}},
-
-    {OPD(2, 0b01, 0x28), 1, X86InstInfo{"VPMULDQ", TYPE_UNDEC, FLAGS_NONE, 0, nullptr}},
-    {OPD(2, 0b01, 0x29), 1, X86InstInfo{"VPCMPEQQ", TYPE_UNDEC, FLAGS_NONE, 0, nullptr}},
-    {OPD(2, 0b01, 0x2A), 1, X86InstInfo{"VMOVNTDQA", TYPE_UNDEC, FLAGS_NONE, 0, nullptr}},
-    {OPD(2, 0b01, 0x2B), 1, X86InstInfo{"VPACKUSDW", TYPE_UNDEC, FLAGS_NONE, 0, nullptr}},
-    {OPD(2, 0b01, 0x2C), 1, X86InstInfo{"VMASKMOVPS", TYPE_UNDEC, FLAGS_NONE, 0, nullptr}},
-    {OPD(2, 0b01, 0x2D), 1, X86InstInfo{"VMASKMOVPD", TYPE_UNDEC, FLAGS_NONE, 0, nullptr}},
-    {OPD(2, 0b01, 0x2E), 1, X86InstInfo{"VMASKMOVPS", TYPE_UNDEC, FLAGS_NONE, 0, nullptr}},
-    {OPD(2, 0b01, 0x2F), 1, X86InstInfo{"VMASKMOVPD", TYPE_UNDEC, FLAGS_NONE, 0, nullptr}},
-
-    {OPD(2, 0b01, 0x30), 1, X86InstInfo{"VPMOVZXBW", TYPE_UNDEC, FLAGS_NONE, 0, nullptr}},
-    {OPD(2, 0b01, 0x31), 1, X86InstInfo{"VPMOVZXBD", TYPE_UNDEC, FLAGS_NONE, 0, nullptr}},
-    {OPD(2, 0b01, 0x32), 1, X86InstInfo{"VPMOVZXBQ", TYPE_UNDEC, FLAGS_NONE, 0, nullptr}},
-    {OPD(2, 0b01, 0x33), 1, X86InstInfo{"VPMOVZXWD", TYPE_UNDEC, FLAGS_NONE, 0, nullptr}},
-    {OPD(2, 0b01, 0x34), 1, X86InstInfo{"VPMOVZXWQ", TYPE_UNDEC, FLAGS_NONE, 0, nullptr}},
-    {OPD(2, 0b01, 0x35), 1, X86InstInfo{"VPMOVZXDQ", TYPE_UNDEC, FLAGS_NONE, 0, nullptr}},
-    {OPD(2, 0b01, 0x36), 1, X86InstInfo{"VPERMD", TYPE_UNDEC, FLAGS_NONE, 0, nullptr}},
-    {OPD(2, 0b01, 0x37), 1, X86InstInfo{"VPVMPGTQ", TYPE_UNDEC, FLAGS_NONE, 0, nullptr}},
-
-    {OPD(2, 0b01, 0x38), 1, X86InstInfo{"VPMINSB", TYPE_UNDEC, FLAGS_NONE, 0, nullptr}},
-    {OPD(2, 0b01, 0x39), 1, X86InstInfo{"VPMINSD", TYPE_UNDEC, FLAGS_NONE, 0, nullptr}},
-    {OPD(2, 0b01, 0x3A), 1, X86InstInfo{"VPMINUW", TYPE_UNDEC, FLAGS_NONE, 0, nullptr}},
-    {OPD(2, 0b01, 0x3B), 1, X86InstInfo{"VPMINUD", TYPE_INST, FLAGS_MODRM | FLAGS_XMM_FLAGS, 0, nullptr}},
-    {OPD(2, 0b01, 0x3C), 1, X86InstInfo{"VPMAXSB", TYPE_UNDEC, FLAGS_NONE, 0, nullptr}},
-    {OPD(2, 0b01, 0x3D), 1, X86InstInfo{"VPMAXSD", TYPE_UNDEC, FLAGS_NONE, 0, nullptr}},
-    {OPD(2, 0b01, 0x3E), 1, X86InstInfo{"VPMAXUW", TYPE_UNDEC, FLAGS_NONE, 0, nullptr}},
-    {OPD(2, 0b01, 0x3F), 1, X86InstInfo{"VPMAXUD", TYPE_UNDEC, FLAGS_NONE, 0, nullptr}},
-
-    {OPD(2, 0b01, 0x40), 1, X86InstInfo{"VPMULLD", TYPE_UNDEC, FLAGS_NONE, 0, nullptr}},
-    {OPD(2, 0b01, 0x41), 1, X86InstInfo{"VPHMINPOSUW", TYPE_UNDEC, FLAGS_NONE, 0, nullptr}},
-    {OPD(2, 0b01, 0x45), 1, X86InstInfo{"VPSRLV", TYPE_UNDEC, FLAGS_NONE, 0, nullptr}},
-    {OPD(2, 0b01, 0x46), 1, X86InstInfo{"VPSRAVD", TYPE_UNDEC, FLAGS_NONE, 0, nullptr}},
-    {OPD(2, 0b01, 0x47), 1, X86InstInfo{"VPSLLV", TYPE_UNDEC, FLAGS_NONE, 0, nullptr}},
-
-    {OPD(2, 0b01, 0x58), 1, X86InstInfo{"VPBROADCASTD", TYPE_INST, FLAGS_MODRM, 0, nullptr}},
-    {OPD(2, 0b01, 0x59), 1, X86InstInfo{"VPBROADCASTQ", TYPE_INST, FLAGS_MODRM, 0, nullptr}},
-    {OPD(2, 0b01, 0x5A), 1, X86InstInfo{"VBBROADCASTI128", TYPE_INST, FLAGS_MODRM, 0, nullptr}},
-
-    {OPD(2, 0b01, 0x78), 1, X86InstInfo{"VPBROADCASTB", TYPE_INST, FLAGS_MODRM, 0, nullptr}},
-    {OPD(2, 0b01, 0x79), 1, X86InstInfo{"VPBROADCASTW", TYPE_INST, FLAGS_MODRM, 0, nullptr}},
-
-    {OPD(2, 0b01, 0x8C), 1, X86InstInfo{"VPMASKMOV", TYPE_UNDEC, FLAGS_NONE, 0, nullptr}},
-    {OPD(2, 0b01, 0x8E), 1, X86InstInfo{"VPMASKMOV", TYPE_UNDEC, FLAGS_NONE, 0, nullptr}},
-
-    {OPD(2, 0b01, 0x90), 1, X86InstInfo{"VPGATHERD", TYPE_UNDEC, FLAGS_NONE, 0, nullptr}},
-    {OPD(2, 0b01, 0x91), 1, X86InstInfo{"VPGATHERQ", TYPE_UNDEC, FLAGS_NONE, 0, nullptr}},
-    {OPD(2, 0b01, 0x92), 1, X86InstInfo{"VPGATHERD", TYPE_UNDEC, FLAGS_NONE, 0, nullptr}},
-    {OPD(2, 0b01, 0x93), 1, X86InstInfo{"VPGATHERQ", TYPE_UNDEC, FLAGS_NONE, 0, nullptr}},
-
-    {OPD(2, 0b01, 0x96), 1, X86InstInfo{"VFMADDSUB132", TYPE_UNDEC, FLAGS_NONE, 0, nullptr}},
-    {OPD(2, 0b01, 0x97), 1, X86InstInfo{"VFMSUBADD132", TYPE_UNDEC, FLAGS_NONE, 0, nullptr}},
-
-    {OPD(2, 0b01, 0x98), 1, X86InstInfo{"VFMADD132", TYPE_UNDEC, FLAGS_NONE, 0, nullptr}},
-    {OPD(2, 0b01, 0x99), 1, X86InstInfo{"VFMADD132", TYPE_UNDEC, FLAGS_NONE, 0, nullptr}},
-    {OPD(2, 0b01, 0x9A), 1, X86InstInfo{"VFMSUB132", TYPE_UNDEC, FLAGS_NONE, 0, nullptr}},
-    {OPD(2, 0b01, 0x9B), 1, X86InstInfo{"VFMSUB132", TYPE_UNDEC, FLAGS_NONE, 0, nullptr}},
-    {OPD(2, 0b01, 0x9C), 1, X86InstInfo{"VFNMADD132", TYPE_UNDEC, FLAGS_NONE, 0, nullptr}},
-    {OPD(2, 0b01, 0x9D), 1, X86InstInfo{"VFNMADD132", TYPE_UNDEC, FLAGS_NONE, 0, nullptr}},
-    {OPD(2, 0b01, 0x9E), 1, X86InstInfo{"VFNMSUB132", TYPE_UNDEC, FLAGS_NONE, 0, nullptr}},
-    {OPD(2, 0b01, 0x9F), 1, X86InstInfo{"VFNMSUB132", TYPE_UNDEC, FLAGS_NONE, 0, nullptr}},
-
-    {OPD(2, 0b01, 0xA8), 1, X86InstInfo{"VFMADD213", TYPE_UNDEC, FLAGS_NONE, 0, nullptr}},
-    {OPD(2, 0b01, 0xA9), 1, X86InstInfo{"VFMADD213", TYPE_UNDEC, FLAGS_NONE, 0, nullptr}},
-    {OPD(2, 0b01, 0xAA), 1, X86InstInfo{"VFMSUB213", TYPE_UNDEC, FLAGS_NONE, 0, nullptr}},
-    {OPD(2, 0b01, 0xAB), 1, X86InstInfo{"VFMSUB213", TYPE_UNDEC, FLAGS_NONE, 0, nullptr}},
-    {OPD(2, 0b01, 0xAC), 1, X86InstInfo{"VFNMADD213", TYPE_UNDEC, FLAGS_NONE, 0, nullptr}},
-    {OPD(2, 0b01, 0xAD), 1, X86InstInfo{"VFNMADD213", TYPE_UNDEC, FLAGS_NONE, 0, nullptr}},
-    {OPD(2, 0b01, 0xAE), 1, X86InstInfo{"VFNMSUB213", TYPE_UNDEC, FLAGS_NONE, 0, nullptr}},
-    {OPD(2, 0b01, 0xAF), 1, X86InstInfo{"VFNMSUB213", TYPE_UNDEC, FLAGS_NONE, 0, nullptr}},
-
-    {OPD(2, 0b01, 0xB8), 1, X86InstInfo{"VFMADD231", TYPE_UNDEC, FLAGS_NONE, 0, nullptr}},
-    {OPD(2, 0b01, 0xB9), 1, X86InstInfo{"VFMADD231", TYPE_UNDEC, FLAGS_NONE, 0, nullptr}},
-    {OPD(2, 0b01, 0xBA), 1, X86InstInfo{"VFMSUB231", TYPE_UNDEC, FLAGS_NONE, 0, nullptr}},
-    {OPD(2, 0b01, 0xBB), 1, X86InstInfo{"VFMSUB231", TYPE_UNDEC, FLAGS_NONE, 0, nullptr}},
-    {OPD(2, 0b01, 0xBC), 1, X86InstInfo{"VFNMADD231", TYPE_UNDEC, FLAGS_NONE, 0, nullptr}},
-    {OPD(2, 0b01, 0xBD), 1, X86InstInfo{"VFNMADD231", TYPE_UNDEC, FLAGS_NONE, 0, nullptr}},
-    {OPD(2, 0b01, 0xBE), 1, X86InstInfo{"VFNMSUB231", TYPE_UNDEC, FLAGS_NONE, 0, nullptr}},
-    {OPD(2, 0b01, 0xBF), 1, X86InstInfo{"VFNMSUB231", TYPE_UNDEC, FLAGS_NONE, 0, nullptr}},
-
-    {OPD(2, 0b01, 0xA6), 1, X86InstInfo{"VFMADDSUB213", TYPE_UNDEC, FLAGS_NONE, 0, nullptr}},
-    {OPD(2, 0b01, 0xA7), 1, X86InstInfo{"VFMSUBADD213", TYPE_UNDEC, FLAGS_NONE, 0, nullptr}},
-
-    {OPD(2, 0b01, 0xB6), 1, X86InstInfo{"VFMADDSUB231", TYPE_UNDEC, FLAGS_NONE, 0, nullptr}},
-    {OPD(2, 0b01, 0xB7), 1, X86InstInfo{"VFMSUBADD231", TYPE_UNDEC, FLAGS_NONE, 0, nullptr}},
-
-    {OPD(2, 0b01, 0xDB), 1, X86InstInfo{"VAESIMC", TYPE_UNDEC, FLAGS_NONE, 0, nullptr}},
-    {OPD(2, 0b01, 0xDC), 1, X86InstInfo{"VAESENC", TYPE_UNDEC, FLAGS_NONE, 0, nullptr}},
-    {OPD(2, 0b01, 0xDD), 1, X86InstInfo{"VAESENCLAST", TYPE_UNDEC, FLAGS_NONE, 0, nullptr}},
-    {OPD(2, 0b01, 0xDE), 1, X86InstInfo{"VAESDEC", TYPE_UNDEC, FLAGS_NONE, 0, nullptr}},
-    {OPD(2, 0b01, 0xDF), 1, X86InstInfo{"VAESDECLAST", TYPE_UNDEC, FLAGS_NONE, 0, nullptr}},
-
-    {OPD(2, 0b00, 0xF2), 1, X86InstInfo{"ANDN", TYPE_INST, FLAGS_MODRM | FLAGS_VEX_1ST_SRC, 0, nullptr}},
-
-    {OPD(2, 0b00, 0xF3), 1, X86InstInfo{"", TYPE_VEX_GROUP_17, FLAGS_NONE, 0, nullptr}}, // VEX Group 17
-    {OPD(2, 0b01, 0xF3), 1, X86InstInfo{"", TYPE_VEX_GROUP_17, FLAGS_NONE, 0, nullptr}}, // VEX Group 17
-    {OPD(2, 0b10, 0xF3), 1, X86InstInfo{"", TYPE_VEX_GROUP_17, FLAGS_NONE, 0, nullptr}}, // VEX Group 17
-    {OPD(2, 0b11, 0xF3), 1, X86InstInfo{"", TYPE_VEX_GROUP_17, FLAGS_NONE, 0, nullptr}}, // VEX Group 17
-
-    {OPD(2, 0b00, 0xF5), 1, X86InstInfo{"BZHI", TYPE_INST, FLAGS_MODRM | FLAGS_VEX_2ND_SRC, 0, nullptr}},
-    // AMD reference manual is incorrect. PEXT actually maps to 0b10, not 0b01.
-    {OPD(2, 0b10, 0xF5), 1, X86InstInfo{"PEXT", TYPE_INST, FLAGS_MODRM | FLAGS_VEX_1ST_SRC, 0, nullptr}},
-    {OPD(2, 0b11, 0xF5), 1, X86InstInfo{"PDEP", TYPE_INST, FLAGS_MODRM | FLAGS_VEX_1ST_SRC, 0, nullptr}},
-
-    {OPD(2, 0b11, 0xF6), 1, X86InstInfo{"MULX", TYPE_INST, FLAGS_MODRM | FLAGS_VEX_1ST_SRC, 0, nullptr}},
-
-    {OPD(2, 0b00, 0xF7), 1, X86InstInfo{"BEXTR", TYPE_INST, FLAGS_MODRM | FLAGS_VEX_2ND_SRC, 0, nullptr}},
-    {OPD(2, 0b01, 0xF7), 1, X86InstInfo{"SHLX", TYPE_INST, FLAGS_MODRM | FLAGS_VEX_2ND_SRC, 0, nullptr}},
-    {OPD(2, 0b10, 0xF7), 1, X86InstInfo{"SARX", TYPE_INST, FLAGS_MODRM | FLAGS_VEX_2ND_SRC, 0, nullptr}},
-    {OPD(2, 0b11, 0xF7), 1, X86InstInfo{"SHRX", TYPE_INST, FLAGS_MODRM | FLAGS_VEX_2ND_SRC, 0, nullptr}},
-
-    // VEX Map 3
-    {OPD(3, 0b01, 0x00), 1, X86InstInfo{"VPERMQ", TYPE_UNDEC, FLAGS_NONE, 0, nullptr}},
-    {OPD(3, 0b01, 0x01), 1, X86InstInfo{"VPERMPD", TYPE_UNDEC, FLAGS_NONE, 0, nullptr}},
-    {OPD(3, 0b01, 0x02), 1, X86InstInfo{"VPBLENDD", TYPE_UNDEC, FLAGS_NONE, 0, nullptr}},
-    {OPD(3, 0b01, 0x04), 1, X86InstInfo{"VPERMILPS", TYPE_UNDEC, FLAGS_NONE, 0, nullptr}},
-    {OPD(3, 0b01, 0x05), 1, X86InstInfo{"VPERMILPD", TYPE_UNDEC, FLAGS_NONE, 0, nullptr}},
-    {OPD(3, 0b01, 0x06), 1, X86InstInfo{"VPERM2F128", TYPE_UNDEC, FLAGS_NONE, 0, nullptr}},
-
-    {OPD(3, 0b01, 0x08), 1, X86InstInfo{"VROUNDPS", TYPE_UNDEC, FLAGS_NONE, 0, nullptr}},
-    {OPD(3, 0b01, 0x09), 1, X86InstInfo{"VROUNDPD", TYPE_UNDEC, FLAGS_NONE, 0, nullptr}},
-    {OPD(3, 0b01, 0x0A), 1, X86InstInfo{"VROUNDSS", TYPE_UNDEC, FLAGS_NONE, 0, nullptr}},
-    {OPD(3, 0b01, 0x0B), 1, X86InstInfo{"VROUNDSD", TYPE_UNDEC, FLAGS_NONE, 0, nullptr}},
-    {OPD(3, 0b01, 0x0C), 1, X86InstInfo{"VBLENDPS", TYPE_UNDEC, FLAGS_NONE, 0, nullptr}},
-    {OPD(3, 0b01, 0x0D), 1, X86InstInfo{"VBLENDPD", TYPE_UNDEC, FLAGS_NONE, 0, nullptr}},
-    {OPD(3, 0b01, 0x0E), 1, X86InstInfo{"VBLENDW", TYPE_UNDEC, FLAGS_NONE, 0, nullptr}},
-    {OPD(3, 0b01, 0x0F), 1, X86InstInfo{"VPALIGNR", TYPE_INST, FLAGS_MODRM | FLAGS_XMM_FLAGS, 1, nullptr}},
-
-    {OPD(3, 0b01, 0x14), 1, X86InstInfo{"VPEXTRB", TYPE_UNDEC, FLAGS_NONE, 0, nullptr}},
-    {OPD(3, 0b01, 0x15), 1, X86InstInfo{"VPEXTRW", TYPE_UNDEC, FLAGS_NONE, 0, nullptr}},
-    {OPD(3, 0b01, 0x16), 1, X86InstInfo{"VPEXTRD", TYPE_UNDEC, FLAGS_NONE, 0, nullptr}},
-    {OPD(3, 0b01, 0x17), 1, X86InstInfo{"VEXTRACTPS", TYPE_UNDEC, FLAGS_NONE, 0, nullptr}},
-
-    {OPD(3, 0b01, 0x18), 1, X86InstInfo{"VINSERTF128", TYPE_UNDEC, FLAGS_NONE, 0, nullptr}},
-    {OPD(3, 0b01, 0x19), 1, X86InstInfo{"VEXTRACTF128", TYPE_UNDEC, FLAGS_NONE, 0, nullptr}},
-    {OPD(3, 0b01, 0x1D), 1, X86InstInfo{"VCVTPS2PH", TYPE_UNDEC, FLAGS_NONE, 0, nullptr}},
-
-    {OPD(3, 0b01, 0x20), 1, X86InstInfo{"VPINSRB", TYPE_UNDEC, FLAGS_NONE, 0, nullptr}},
-    {OPD(3, 0b01, 0x21), 1, X86InstInfo{"VINSERTPS", TYPE_UNDEC, FLAGS_NONE, 0, nullptr}},
-    {OPD(3, 0b01, 0x22), 1, X86InstInfo{"VPINSRD", TYPE_UNDEC, FLAGS_NONE, 0, nullptr}},
-
-    {OPD(3, 0b01, 0x38), 1, X86InstInfo{"VINSERTI128", TYPE_UNDEC, FLAGS_NONE, 0, nullptr}},
-    {OPD(3, 0b01, 0x39), 1, X86InstInfo{"VEXTRACTI128", TYPE_UNDEC, FLAGS_NONE, 0, nullptr}},
-
-    {OPD(3, 0b01, 0x40), 1, X86InstInfo{"VDPPS", TYPE_UNDEC, FLAGS_NONE, 0, nullptr}},
-    {OPD(3, 0b01, 0x41), 1, X86InstInfo{"VDPPD", TYPE_UNDEC, FLAGS_NONE, 0, nullptr}},
-    {OPD(3, 0b01, 0x42), 1, X86InstInfo{"VMPSADBW", TYPE_UNDEC, FLAGS_NONE, 0, nullptr}},
-    {OPD(3, 0b01, 0x44), 1, X86InstInfo{"VPCLMULQDQ", TYPE_INST, GenFlagsSameSize(SIZE_128BIT) | FLAGS_MODRM | FLAGS_VEX_1ST_SRC | FLAGS_XMM_FLAGS, 1, nullptr}},
-    {OPD(3, 0b01, 0x46), 1, X86InstInfo{"VPERM2I128", TYPE_UNDEC, FLAGS_NONE, 0, nullptr}},
-
-    {OPD(3, 0b01, 0x48), 1, X86InstInfo{"VPERMILzz2PS", TYPE_UNDEC, FLAGS_NONE, 0, nullptr}},
-    {OPD(3, 0b01, 0x49), 1, X86InstInfo{"VPERMILzz2PD", TYPE_UNDEC, FLAGS_NONE, 0, nullptr}},
-    {OPD(3, 0b01, 0x4A), 1, X86InstInfo{"VBLENDVPS", TYPE_UNDEC, FLAGS_NONE, 0, nullptr}},
-    {OPD(3, 0b01, 0x4B), 1, X86InstInfo{"VBLENDVPD", TYPE_UNDEC, FLAGS_NONE, 0, nullptr}},
-    {OPD(3, 0b01, 0x4C), 1, X86InstInfo{"VBLENDVB", TYPE_UNDEC, FLAGS_NONE, 0, nullptr}},
-
-    {OPD(3, 0b01, 0x5C), 1, X86InstInfo{"VFMADDSUBPS", TYPE_UNDEC, FLAGS_NONE, 0, nullptr}},
-    {OPD(3, 0b01, 0x5D), 1, X86InstInfo{"VFMADDSUBPD", TYPE_UNDEC, FLAGS_NONE, 0, nullptr}},
-    {OPD(3, 0b01, 0x5E), 1, X86InstInfo{"VMFSUBADDPS", TYPE_UNDEC, FLAGS_NONE, 0, nullptr}},
-    {OPD(3, 0b01, 0x5F), 1, X86InstInfo{"VFMSUBADDPD", TYPE_UNDEC, FLAGS_NONE, 0, nullptr}},
-
-    {OPD(3, 0b01, 0x60), 1, X86InstInfo{"VPCMPESTRM", TYPE_UNDEC, FLAGS_NONE, 0, nullptr}},
-    {OPD(3, 0b01, 0x61), 1, X86InstInfo{"VPCMPESTRI", TYPE_UNDEC, FLAGS_NONE, 0, nullptr}},
-    {OPD(3, 0b01, 0x62), 1, X86InstInfo{"VPCMPISTRM", TYPE_UNDEC, FLAGS_NONE, 0, nullptr}},
-    {OPD(3, 0b01, 0x63), 1, X86InstInfo{"VPCMPISTRI", TYPE_INST, FLAGS_MODRM | FLAGS_XMM_FLAGS, 1, nullptr}},
-
-    {OPD(3, 0b01, 0x68), 1, X86InstInfo{"VFMADDPS", TYPE_UNDEC, FLAGS_NONE, 0, nullptr}},
-    {OPD(3, 0b01, 0x69), 1, X86InstInfo{"VFMADDPD", TYPE_UNDEC, FLAGS_NONE, 0, nullptr}},
-    {OPD(3, 0b01, 0x6A), 1, X86InstInfo{"VFMADDSS", TYPE_UNDEC, FLAGS_NONE, 0, nullptr}},
-    {OPD(3, 0b01, 0x6B), 1, X86InstInfo{"VFMADDSD", TYPE_UNDEC, FLAGS_NONE, 0, nullptr}},
-    {OPD(3, 0b01, 0x6C), 1, X86InstInfo{"VFMSUBPS", TYPE_UNDEC, FLAGS_NONE, 0, nullptr}},
-    {OPD(3, 0b01, 0x6D), 1, X86InstInfo{"VFMSUBPD", TYPE_UNDEC, FLAGS_NONE, 0, nullptr}},
-    {OPD(3, 0b01, 0x6E), 1, X86InstInfo{"VFMSUBSS", TYPE_UNDEC, FLAGS_NONE, 0, nullptr}},
-    {OPD(3, 0b01, 0x6F), 1, X86InstInfo{"VFMSUBSD", TYPE_UNDEC, FLAGS_NONE, 0, nullptr}},
-
-    {OPD(3, 0b01, 0x78), 1, X86InstInfo{"VFNMADDPS", TYPE_UNDEC, FLAGS_NONE, 0, nullptr}},
-    {OPD(3, 0b01, 0x79), 1, X86InstInfo{"VFNMADDPD", TYPE_UNDEC, FLAGS_NONE, 0, nullptr}},
-    {OPD(3, 0b01, 0x7A), 1, X86InstInfo{"VFNMADDSS", TYPE_UNDEC, FLAGS_NONE, 0, nullptr}},
-    {OPD(3, 0b01, 0x7B), 1, X86InstInfo{"VFNMADDSD", TYPE_UNDEC, FLAGS_NONE, 0, nullptr}},
-    {OPD(3, 0b01, 0x7C), 1, X86InstInfo{"VFNMSUBPS", TYPE_UNDEC, FLAGS_NONE, 0, nullptr}},
-    {OPD(3, 0b01, 0x7D), 1, X86InstInfo{"VFNMSUBPD", TYPE_UNDEC, FLAGS_NONE, 0, nullptr}},
-    {OPD(3, 0b01, 0x7E), 1, X86InstInfo{"VFNMSUBSS", TYPE_UNDEC, FLAGS_NONE, 0, nullptr}},
-    {OPD(3, 0b01, 0x7F), 1, X86InstInfo{"VFNMSUBSD", TYPE_UNDEC, FLAGS_NONE, 0, nullptr}},
-
-    {OPD(3, 0b01, 0xDF), 1, X86InstInfo{"VAESKEYGENASSIST", TYPE_UNDEC, FLAGS_NONE, 0, nullptr}},
-
-    {OPD(3, 0b11, 0xF0), 1, X86InstInfo{"RORX", TYPE_INST, FLAGS_MODRM, 1, nullptr}},
-
-    // VEX Map 4 - 31 (Reserved)
-  };
-#undef OPD
-
-#define OPD(group, pp, opcode) (((group - TYPE_VEX_GROUP_12) << 4) | (pp << 3) | (opcode))
-  static constexpr U8U8InfoStruct VEXGroupTable[] = {
-    {OPD(TYPE_VEX_GROUP_12, 1, 0b010), 1, X86InstInfo{"VPSRLW",   TYPE_UNDEC, FLAGS_MODRM, 0, nullptr}},
-    {OPD(TYPE_VEX_GROUP_12, 1, 0b100), 1, X86InstInfo{"VPSRAW",   TYPE_UNDEC, FLAGS_MODRM, 0, nullptr}},
-    {OPD(TYPE_VEX_GROUP_12, 1, 0b110), 1, X86InstInfo{"VPSLLW",   TYPE_UNDEC, FLAGS_MODRM, 0, nullptr}},
-
-    {OPD(TYPE_VEX_GROUP_13, 1, 0b010), 1, X86InstInfo{"VPSRLD",   TYPE_UNDEC, FLAGS_MODRM, 0, nullptr}},
-    {OPD(TYPE_VEX_GROUP_13, 1, 0b100), 1, X86InstInfo{"VPSRAD",   TYPE_UNDEC, FLAGS_MODRM, 0, nullptr}},
-    {OPD(TYPE_VEX_GROUP_13, 1, 0b110), 1, X86InstInfo{"VPSLLD",   TYPE_UNDEC, FLAGS_MODRM, 0, nullptr}},
-
-    {OPD(TYPE_VEX_GROUP_14, 1, 0b010), 1, X86InstInfo{"VPSRLQ",   TYPE_INST, FLAGS_MODRM | FLAGS_XMM_FLAGS, 1, nullptr}},
-    {OPD(TYPE_VEX_GROUP_14, 1, 0b011), 1, X86InstInfo{"VPSRLDQ",  TYPE_INST, FLAGS_MODRM | FLAGS_XMM_FLAGS, 1, nullptr}},
-    {OPD(TYPE_VEX_GROUP_14, 1, 0b110), 1, X86InstInfo{"VPSLLQ",   TYPE_INST, FLAGS_MODRM | FLAGS_XMM_FLAGS, 1, nullptr}},
-    {OPD(TYPE_VEX_GROUP_14, 1, 0b111), 1, X86InstInfo{"VPSLLDQ",  TYPE_INST, FLAGS_MODRM | FLAGS_XMM_FLAGS, 1, nullptr}},
-
-    {OPD(TYPE_VEX_GROUP_15, 1, 0b010), 1, X86InstInfo{"VLDMXCSR", TYPE_UNDEC, FLAGS_MODRM, 0, nullptr}},
-    {OPD(TYPE_VEX_GROUP_15, 1, 0b011), 1, X86InstInfo{"VSTMXCSR", TYPE_UNDEC, FLAGS_MODRM, 0, nullptr}},
-
-    {OPD(TYPE_VEX_GROUP_17, 0, 0b001), 1, X86InstInfo{"BLSR",     TYPE_INST, FLAGS_MODRM | FLAGS_VEX_DST, 0, nullptr}},
-    {OPD(TYPE_VEX_GROUP_17, 0, 0b010), 1, X86InstInfo{"BLSMSK",   TYPE_INST, FLAGS_MODRM | FLAGS_VEX_DST, 0, nullptr}},
-    {OPD(TYPE_VEX_GROUP_17, 0, 0b011), 1, X86InstInfo{"BLSI",     TYPE_INST, FLAGS_MODRM | FLAGS_VEX_DST, 0, nullptr}},
-  };
-#undef OPD
-
-  GenerateTable(&VEXTableOps.at(0), VEXTable, std::size(VEXTable));
-  GenerateTable(&VEXTableGroupOps.at(0), VEXGroupTable, std::size(VEXGroupTable));
-}
-}
@@ -1,104 +0,0 @@
-/*
-$info$
-tags: frontend|x86-tables
-$end_info$
-*/
-
-#pragma once
-#include <FEXCore/Debug/X86Tables.h>
-#include <FEXCore/Core/Context.h>
-
-#include <FEXCore/Utils/LogManager.h>
-
-namespace FEXCore::X86Tables {
-
-#ifndef NDEBUG
-extern uint64_t Total;
-extern uint64_t NumInsts;
-#endif
-
-template <typename OpcodeType>
-struct X86TablesInfoStruct {
-  OpcodeType first;
-  uint8_t second;
-  X86InstInfo Info;
-};
-using U8U8InfoStruct = X86TablesInfoStruct<uint8_t>;
-using U16U8InfoStruct = X86TablesInfoStruct<uint16_t>;
-
-template<typename OpcodeType>
-static inline void GenerateTable(X86InstInfo *FinalTable, X86TablesInfoStruct<OpcodeType> const *LocalTable, size_t TableSize) {
-  for (size_t j = 0; j < TableSize; ++j) {
-    X86TablesInfoStruct<OpcodeType> const &Op = LocalTable[j];
-    auto OpNum = Op.first;
-    X86InstInfo const &Info = Op.Info;
-    for (uint32_t i = 0; i < Op.second; ++i) {
-      LOGMAN_THROW_AA_FMT(FinalTable[OpNum + i].Type == TYPE_UNKNOWN, "Duplicate Entry {}->{}", FinalTable[OpNum + i].Name, Info.Name);
-      FinalTable[OpNum + i] = Info;
-#ifndef NDEBUG
-      ++Total;
-      if (Info.Type == TYPE_INST)
-        NumInsts++;
-#endif
-    }
-  }
-};
-
-template<typename OpcodeType>
-static inline void GenerateTableWithCopy(X86InstInfo *FinalTable, X86TablesInfoStruct<OpcodeType> const *LocalTable, size_t TableSize, X86InstInfo *OtherLocal) {
-  for (size_t j = 0; j < TableSize; ++j) {
-    X86TablesInfoStruct<OpcodeType> const &Op = LocalTable[j];
-    auto OpNum = Op.first;
-    X86InstInfo const &Info = Op.Info;
-    for (uint32_t i = 0; i < Op.second; ++i) {
-      LOGMAN_THROW_AA_FMT(FinalTable[OpNum + i].Type == TYPE_UNKNOWN, "Duplicate Entry {}->{}", FinalTable[OpNum + i].Name, Info.Name);
-      if (Info.Type == TYPE_COPY_OTHER) {
-        FinalTable[OpNum + i] = OtherLocal[OpNum + i];
-      }
-      else {
-        FinalTable[OpNum + i] = Info;
-#ifndef NDEBUG
-        ++Total;
-        if (Info.Type == TYPE_INST)
-          NumInsts++;
-#endif
-      }
-    }
-  }
-};
-
-template<typename OpcodeType>
-static inline void GenerateX87Table(X86InstInfo *FinalTable, X86TablesInfoStruct<OpcodeType> const *LocalTable, size_t TableSize) {
-  for (size_t j = 0; j < TableSize; ++j) {
-    X86TablesInfoStruct<OpcodeType> const &Op = LocalTable[j];
-    auto OpNum = Op.first;
-    X86InstInfo const &Info = Op.Info;
-    for (uint32_t i = 0; i < Op.second; ++i) {
-      LOGMAN_THROW_AA_FMT(FinalTable[OpNum + i].Type == TYPE_UNKNOWN, "Duplicate Entry {}->{}", FinalTable[OpNum + i].Name, Info.Name);
-      if ((OpNum & 0b11'000'000) == 0b11'000'000) {
-        // If the mod field is 0b11 then it is a regular op
-        FinalTable[OpNum + i] = Info;
-      }
-      else {
-        // If the mod field is !0b11 then this instruction is duplicated through the whole mod [0b00, 0b10] range
-        // and the modrm.rm space because that is used part of the instruction encoding
-        LOGMAN_THROW_AA_FMT((OpNum & 0b11'000'000) == 0, "Only support mod field of zero in this path");
-        for (uint16_t mod = 0b00'000'000; mod < 0b11'000'000; mod += 0b01'000'000) {
-          for (uint16_t rm = 0b000; rm < 0b1'000; ++rm) {
-            FinalTable[(OpNum | mod | rm) + i] = Info;
-          }
-        }
-      }
-#ifndef NDEBUG
-        ++Total;
-        if (Info.Type == TYPE_INST)
-          NumInsts++;
-#endif
-    }
-  }
-};
-
-void InitializeInfoTables(Context::OperatingMode Mode);
-
-}
-
@@ -1,38 +0,0 @@
-/*
-$info$
-tags: glue|thunks
-$end_info$
-*/
-
-#pragma once
-
-#include <FEXCore/IR/IR.h>
-
-#include <vector>
-
-namespace FEXCore::Context {
-  struct Context;
-}
-
-namespace FEXCore::Core {
-  struct InternalThreadState;
-}
-
-namespace FEXCore::IR {
-  struct SHA256Sum;
-}
-
-namespace FEXCore {
-    typedef void ThunkedFunction(void* ArgsRv);
-
-    class ThunkHandler {
-    public:
-        virtual ThunkedFunction* LookupThunk(const IR::SHA256Sum &sha256) = 0;
-        virtual void RegisterTLSState(FEXCore::Core::InternalThreadState *Thread) = 0;
-        virtual ~ThunkHandler() { }
-
-        static ThunkHandler* Create();
-
-        virtual void AppendThunkDefinitions(std::vector<FEXCore::IR::ThunkDefinition> const& Definitions) = 0;
-    };
-};
@@ -1,34 +0,0 @@
-#pragma once
-
-#include <memory>
-
-namespace FEXCore::Utils {
-class IntrusivePooledAllocator;
-}
-
-namespace FEXCore::IR {
-class Pass;
-class RegisterAllocationPass;
-class RegisterAllocationData;
-
-std::unique_ptr<FEXCore::IR::Pass> CreateConstProp(bool InlineConstants, bool SupportsTSOImm9);
-std::unique_ptr<FEXCore::IR::Pass> CreateContextLoadStoreElimination(bool SupportsAVX);
-std::unique_ptr<FEXCore::IR::Pass> CreateSyscallOptimization();
-std::unique_ptr<FEXCore::IR::Pass> CreateDeadFlagCalculationEliminination();
-std::unique_ptr<FEXCore::IR::Pass> CreateDeadStoreElimination(bool SupportsAVX);
-std::unique_ptr<FEXCore::IR::Pass> CreatePassDeadCodeElimination();
-std::unique_ptr<FEXCore::IR::Pass> CreateIRCompaction(FEXCore::Utils::IntrusivePooledAllocator &Allocator);
-std::unique_ptr<FEXCore::IR::RegisterAllocationPass> CreateRegisterAllocationPass(FEXCore::IR::Pass* CompactionPass,
-                                                                                  bool OptimizeSRA,
-                                                                                  bool SupportsAVX);
-std::unique_ptr<FEXCore::IR::Pass> CreateStaticRegisterAllocationPass(bool SupportsAVX);
-std::unique_ptr<FEXCore::IR::Pass> CreateLongDivideEliminationPass();
-
-namespace Validation {
-std::unique_ptr<FEXCore::IR::Pass> CreateIRValidation();
-std::unique_ptr<FEXCore::IR::Pass> CreateRAValidation();
-std::unique_ptr<FEXCore::IR::Pass> CreatePhiValidation();
-std::unique_ptr<FEXCore::IR::Pass> CreateValueDominanceValidation();
-}
-}
-
@@ -1,78 +0,0 @@
-/*
-$info$
-tags: ir|opts
-desc: Sanity checking pass
-$end_info$
-*/
-
-#include <FEXCore/IR/IR.h>
-#include <FEXCore/IR/IREmitter.h>
-#include <FEXCore/IR/IntrusiveIRList.h>
-#include <FEXCore/Utils/LogManager.h>
-#include <FEXCore/Utils/Profiler.h>
-
-#include "Interface/IR/PassManager.h"
-
-#include <memory>
-#include <sstream>
-#include <string>
-
-namespace FEXCore::IR::Validation {
-
-class PhiValidation final : public FEXCore::IR::Pass {
-public:
-  bool Run(IREmitter *IREmit) override;
-};
-
-bool PhiValidation::Run(IREmitter *IREmit) {
-  FEXCORE_PROFILE_SCOPED("PassManager::PHIValidation");
-
-  bool HadError = false;
-  auto CurrentIR = IREmit->ViewIR();
-
-  std::ostringstream Errors;
-
-  // Walk the list and calculate the control flow
-  for (auto [BlockNode, BlockHeader] : CurrentIR.GetBlocks()) {
-
-    bool FoundNonPhi{};
-
-    for (auto [CodeNode, IROp] : CurrentIR.GetCode(BlockNode)) {
-
-      switch (IROp->Op) {
-        // BEGINBLOCK doesn't matter for us
-        case IR::OP_BEGINBLOCK: break;
-        case IR::OP_PHIVALUE:
-        case IR::OP_PHI: {
-          if (FoundNonPhi) {
-            // If we have found a non-phi IR op and then had a Phi or PhiValue value then this is a programming mistake
-            // PHI values MUST be defined at the top of the block only
-            HadError |= true;
-            Errors << "Phi %ssa" << CurrentIR.GetID(CodeNode) << ": Was defined after non-phi operations. Which is invalid!" << std::endl;
-          }
-
-          // Check all the phi values to ensure they have the same type
-          break;
-        }
-        default:
-          FoundNonPhi = true;
-          break;
-      }
-    }
-  }
-
-  if (HadError) {
-    std::stringstream Out;
-    FEXCore::IR::Dump(&Out, &CurrentIR, nullptr);
-    Out << "Errors:" << std::endl << Errors.str() << std::endl;
-    LogMan::Msg::EFmt("{}", Out.str());
-  }
-
-  return false;
-}
-
-std::unique_ptr<FEXCore::IR::Pass> CreatePhiValidation() {
-  return std::make_unique<PhiValidation>();
-}
-
-}
@@ -1,131 +0,0 @@
-/*
-$info$
-tags: ir|opts
-desc: Replaces Load/StoreContext with Load/StoreReg for SRA regs
-$end_info$
-*/
-
-#include "Interface/IR/PassManager.h"
-#include <FEXCore/Core/CoreState.h>
-#include <FEXCore/IR/IR.h>
-#include <FEXCore/IR/IREmitter.h>
-#include <FEXCore/IR/IntrusiveIRList.h>
-#include <FEXCore/Utils/LogManager.h>
-#include <FEXCore/Utils/Profiler.h>
-
-#include <memory>
-#include <stddef.h>
-#include <stdint.h>
-
-namespace FEXCore::IR {
-
-class StaticRegisterAllocationPass final : public FEXCore::IR::Pass {
-public:
-  explicit StaticRegisterAllocationPass(bool SupportsAVX_) : SupportsAVX{SupportsAVX_} {}
-
-  bool Run(IREmitter *IREmit) override;
-
-private:
-  bool SupportsAVX;
-
-  bool IsStaticAllocGpr(uint32_t Offset, RegisterClassType Class) const {
-    const auto begin = offsetof(Core::CPUState, gregs[0]);
-    const auto end = offsetof(Core::CPUState, gregs[16]);
-
-    if (Offset >= begin && Offset < end) {
-      const auto reg = (Offset - begin) / Core::CPUState::GPR_REG_SIZE;
-      LOGMAN_THROW_AA_FMT(Class.Val == IR::GPRClass.Val, "unexpected Class {}", Class);
-
-      // 0..15 -> 16 in total
-      return reg < Core::CPUState::NUM_GPRS;
-    }
-
-    return false;
-  }
-
-  bool IsStaticAllocFpr(uint32_t Offset, RegisterClassType Class, bool AllowGpr) const {
-    const auto [begin, end] = [this]() -> std::pair<ptrdiff_t, ptrdiff_t> {
-      if (SupportsAVX) {
-        return {
-          offsetof(Core::CPUState, xmm.avx.data[0][0]),
-          offsetof(Core::CPUState, xmm.avx.data[16][0]),
-        };
-      } else {
-        return {
-          offsetof(Core::CPUState, xmm.sse.data[0][0]),
-          offsetof(Core::CPUState, xmm.sse.data[16][0]),
-        };
-      }
-    }();
-
-    if (Offset >= begin && Offset < end) {
-      const auto size = SupportsAVX ? Core::CPUState::XMM_AVX_REG_SIZE
-                                    : Core::CPUState::XMM_SSE_REG_SIZE;
-      const auto reg = (Offset - begin) / size;
-      LOGMAN_THROW_AA_FMT(Class.Val == IR::FPRClass.Val || (AllowGpr && Class.Val == IR::GPRClass.Val), "unexpected Class {}, AllowGpr {}", Class, AllowGpr);
-
-      // 0..15 -> 16 in total
-      return reg < Core::CPUState::NUM_XMMS;
-    }
-
-    return false;
-  }
-};
-
-/**
- * @brief This pass replaces Load/Store Context with Load/Store Register for Statically Mapped registers. It also does some validation.
- *
- */
-bool StaticRegisterAllocationPass::Run(IREmitter *IREmit) {
-  FEXCORE_PROFILE_SCOPED("PassManager::SRA");
-
-  auto CurrentIR = IREmit->ViewIR();
-
-  for (auto [BlockNode, BlockIROp] : CurrentIR.GetBlocks()) {
-      for (auto [CodeNode, IROp] : CurrentIR.GetCode(BlockNode)) {
-        IREmit->SetWriteCursor(CodeNode);
-
-        if (IROp->Op == OP_LOADCONTEXT) {
-            auto Op = IROp->CW<IR::IROp_LoadContext>();
-
-            if (IsStaticAllocGpr(Op->Offset, Op->Class) || IsStaticAllocFpr(Op->Offset, Op->Class, true)) {
-              auto GeneralClass = Op->Class;
-              if (IsStaticAllocFpr(Op->Offset, GeneralClass, true) && GeneralClass == GPRClass) {
-                GeneralClass = FPRClass;
-              }
-              auto StaticClass = GeneralClass == GPRClass ? GPRFixedClass : FPRFixedClass;
-              OrderedNode *sraReg = IREmit->_LoadRegister(false, Op->Offset, GeneralClass, StaticClass, Op->Header.Size);
-              if (GeneralClass != Op->Class) {
-                sraReg = IREmit->_VExtractToGPR(Op->Header.Size, Op->Header.Size, sraReg, 0);
-              }
-              IREmit->ReplaceAllUsesWith(CodeNode, sraReg);
-            }
-        } if (IROp->Op == OP_STORECONTEXT) {
-            auto Op = IROp->CW<IR::IROp_StoreContext>();
-
-            if (IsStaticAllocGpr(Op->Offset, Op->Class) || IsStaticAllocFpr(Op->Offset, Op->Class, true)) {
-              auto val = IREmit->UnwrapNode(Op->Value);
-
-              auto GeneralClass = Op->Class;
-              if (IsStaticAllocFpr(Op->Offset, GeneralClass, true) && GeneralClass == GPRClass) {
-                val = IREmit->_VCastFromGPR(Op->Header.Size, Op->Header.Size, val);
-                GeneralClass = FPRClass;
-              }
-
-              auto StaticClass = GeneralClass == GPRClass ? GPRFixedClass : FPRFixedClass;
-              IREmit->_StoreRegister(val, false, Op->Offset, GeneralClass, StaticClass, Op->Header.Size);
-
-              IREmit->Remove(CodeNode);
-            }
-        }
-    }
-  }
-
-  return true;
-}
-
-std::unique_ptr<FEXCore::IR::Pass> CreateStaticRegisterAllocationPass(bool SupportsAVX) {
-  return std::make_unique<StaticRegisterAllocationPass>(SupportsAVX);
-}
-
-}
@@ -1,51 +0,0 @@
-#include <string>
-#include <vector>
-#include <filesystem>
-#include <fstream>
-
-namespace FEXCore::FileLoading {
-bool LoadFile(std::vector<char> &Data, const std::string &Filepath, size_t FixedSize) {
-  std::fstream ConfigFile;
-  ConfigFile.open(Filepath, std::ios::in);
-
-  if (!ConfigFile.is_open()) {
-    return false;
-  }
-
-  size_t FileSize{};
-
-  if (FixedSize == 0) {
-    if (!ConfigFile.seekg(0, std::fstream::end)) {
-      return false;
-    }
-
-    FileSize = ConfigFile.tellg();
-    if (ConfigFile.fail()) {
-      return false;
-    }
-
-    if (!ConfigFile.seekg(0, std::fstream::beg)) {
-      return false;
-    }
-  }
-  else {
-    FileSize = FixedSize;
-  }
-
-  if (FileSize > 0) {
-    Data.resize(FileSize);
-    if (!ConfigFile.read(&Data.at(0), FileSize)) {
-      // Probably means permissions aren't set. Just early exit
-      return false;
-    }
-    ConfigFile.close();
-  }
-  else {
-    return false;
-  }
-
-  return true;
-}
-
-
-}
@@ -1,18 +0,0 @@
-#pragma once
-#include <string>
-#include <vector>
-#include <filesystem>
-#include <fstream>
-
-namespace FEXCore::FileLoading {
-  /**
-   * @brief Loads a filepath in to a vector of data
-   *
-   * @param Data The vector to load the file data in to
-   * @param Filepath The filepath to load
-   *
-   * @return true on file loaded, false on failure
-   */
-  bool LoadFile(std::vector<char> &Data, const std::string &Filepath, size_t FixedSize = 0);
-}
-
@@ -1,81 +0,0 @@
-/*
-$info$
-tags: glue|log-manager
-$end_info$
-*/
-
-#include <FEXCore/Utils/CompilerDefs.h>
-#include <FEXCore/Utils/LogManager.h>
-
-#include <alloca.h>
-#include <fmt/format.h>
-#include <cstdarg>
-#include <cstdio>
-#include <string>
-#include <vector>
-
-namespace LogMan {
-
-namespace Throw {
-std::vector<ThrowHandler> Handlers;
-void InstallHandler(ThrowHandler Handler) { Handlers.emplace_back(Handler); }
-void UnInstallHandlers() { Handlers.clear(); }
-
-void MFmt(const char *fmt, const fmt::format_args& args) {
-  auto msg = fmt::vformat(fmt, args);
-
-  for (auto& Handler : Handlers) {
-    Handler(msg.c_str());
-  }
-
-  FEX_TRAP_EXECUTION;
-}
-} // namespace Throw
-
-namespace Msg {
-std::vector<MsgHandler> Handlers;
-void InstallHandler(MsgHandler Handler) { Handlers.emplace_back(Handler); }
-void UnInstallHandlers() { Handlers.clear(); }
-
-static void M(DebugLevels Level, const char *fmt, va_list args) {
-  size_t MsgSize = 1024;
-  char *Buffer = reinterpret_cast<char*>(alloca(MsgSize));
-  va_list argsCopy;
-  va_copy(argsCopy, args);
-  size_t Return = vsnprintf(Buffer, MsgSize, fmt, argsCopy);
-  va_end(argsCopy);
-  if (Return >= MsgSize) {
-    // Allocate a bigger size on failure
-    MsgSize = Return;
-    Buffer = reinterpret_cast<char*>(alloca(MsgSize));
-    va_end(argsCopy);
-    va_copy(argsCopy, args);
-    vsnprintf(Buffer, MsgSize, fmt, argsCopy);
-    va_end(argsCopy);
-  }
-  for (auto &Handler : Handlers) {
-    Handler(Level, Buffer);
-  }
-}
-
-void D(const char *fmt, ...) {
-  if (MSG_LEVEL < DEBUG) {
-    return;
-  }
-
-  va_list args;
-  va_start(args, fmt);
-  M(DEBUG, fmt, args);
-  va_end(args);
-}
-
-void MFmtImpl(DebugLevels level, const char* fmt, const fmt::format_args& args) {
-  const auto msg = fmt::vformat(fmt, args);
-
-  for (auto& Handler : Handlers) {
-    Handler(level, msg.c_str());
-  }
-}
-
-} // namespace Msg
-} // namespace LogMan
@@ -1,220 +0,0 @@
-#include <FEXCore/Utils/Allocator.h>
-#include <FEXCore/Utils/LogManager.h>
-#include <FEXCore/Utils/Threads.h>
-
-#include <alloca.h>
-#include <cstring>
-#include <functional>
-#include <memory>
-#include <mutex>
-#include <pthread.h>
-#include <stdint.h>
-#include <sys/mman.h>
-#include <sys/signal.h>
-#include <sys/syscall.h>
-#include <deque>
-#include <unistd.h>
-
-namespace FEXCore::Threads {
-  // Stack pool handling
-  struct StackPoolItem {
-    void *Ptr;
-    size_t Size;
-  };
-  std::mutex DeadStackPoolMutex{};
-  std::mutex LiveStackPoolMutex{};
-
-  static std::deque<StackPoolItem> DeadStackPool{};
-  static std::deque<StackPoolItem> LiveStackPool{};
-
-  void *AllocateStackObject(size_t Size) {
-    std::lock_guard lk{DeadStackPoolMutex};
-    if (DeadStackPool.size() == 0) {
-      // Nothing in the pool, just allocate
-      return FEXCore::Allocator::mmap(nullptr, Size, PROT_READ | PROT_WRITE, MAP_PRIVATE | MAP_ANONYMOUS, -1, 0);
-    }
-
-    // Keep the first item in the stack pool
-    auto Result = DeadStackPool.front().Ptr;
-    DeadStackPool.pop_front();
-
-    // Erase the rest as a garbage collection step
-    for (auto &Item : DeadStackPool) {
-      FEXCore::Allocator::munmap(Item.Ptr, Item.Size);
-    }
-    return Result;
-  }
-
-  void AddStackToDeadPool(void *Ptr, size_t Size) {
-    std::lock_guard lk{DeadStackPoolMutex};
-    DeadStackPool.emplace_back(StackPoolItem{Ptr, Size});
-  }
-
-  void AddStackToLivePool(void *Ptr, size_t Size) {
-    std::lock_guard lk{LiveStackPoolMutex};
-    LiveStackPool.emplace_back(StackPoolItem{Ptr, Size});
-  }
-
-  void RemoveStackFromLivePool(void *Ptr) {
-    std::lock_guard lk{LiveStackPoolMutex};
-    for (auto it = LiveStackPool.begin(); it != LiveStackPool.end(); ++it) {
-      if (it->Ptr == Ptr) {
-        LiveStackPool.erase(it);
-        return;
-      }
-    }
-  }
-
-  void DeallocateStackObject(void *Ptr, size_t Size) {
-    RemoveStackFromLivePool(Ptr);
-    AddStackToDeadPool(Ptr, Size);
-  }
-
-  void Shutdown() {
-    std::lock_guard lk{DeadStackPoolMutex};
-    std::lock_guard lk2{LiveStackPoolMutex};
-    // Erase all the dead stack pools
-    for (auto &Item : DeadStackPool) {
-      FEXCore::Allocator::munmap(Item.Ptr, Item.Size);
-    }
-
-    // Now clean up any that are considered to still be live
-    // We are in shutdown phase, everything in the process is dead
-    for (auto &Item : LiveStackPool) {
-      FEXCore::Allocator::munmap(Item.Ptr, Item.Size);
-    }
-
-    DeadStackPool.clear();
-    LiveStackPool.clear();
-  }
-
-  void *InitializeThread(void *Ptr);
-
-  class PThread final : public Thread {
-    public:
-    PThread(FEXCore::Threads::ThreadFunc Func, void *Arg)
-      : UserFunc {Func}
-      , UserArg {Arg} {
-      pthread_attr_t Attr{};
-      Stack = AllocateStackObject(STACK_SIZE);
-      AddStackToLivePool(Stack, STACK_SIZE);
-      pthread_attr_init(&Attr);
-      pthread_attr_setstack(&Attr, Stack, STACK_SIZE);
-      pthread_create(&Thread, &Attr, Func, Arg);
-
-      pthread_attr_destroy(&Attr);
-    }
-
-    bool joinable() override {
-      pthread_attr_t Attr{};
-      if (pthread_getattr_np(Thread, &Attr) == 0) {
-        int AttachState{};
-        if (pthread_attr_getdetachstate(&Attr, &AttachState) == 0) {
-          if (AttachState == PTHREAD_CREATE_JOINABLE) {
-            return true;
-          }
-        }
-      }
-      return false;
-    }
-
-    bool join(void **ret) override {
-      return pthread_join(Thread, ret) == 0;
-    }
-
-    bool detach() override {
-      return pthread_detach(Thread) == 0;
-    }
-
-    bool IsSelf() override {
-      auto self = pthread_self();
-      return self == Thread;
-    }
-
-    void *Execute() {
-      return UserFunc(UserArg);
-    }
-
-    void FreeStack() {
-      DeallocateStackObject(Stack, STACK_SIZE);
-    }
-
-    private:
-    pthread_t Thread;
-    FEXCore::Threads::ThreadFunc UserFunc;
-    void *UserArg;
-    void *Stack{};
-    constexpr static size_t STACK_SIZE = 8 * 1024 * 1024;
-  };
-
-  void *InitializeThread(void *Ptr) {
-    PThread *Thread{reinterpret_cast<PThread*>(Ptr)};
-
-    // Run the user function
-    void *Result = Thread->Execute();
-
-    // Put the stack back in to the stack pool
-    Thread->FreeStack();
-    return Result;
-  }
-
-  std::unique_ptr<FEXCore::Threads::Thread> CreateThread_PThread(
-    ThreadFunc Func,
-    void* Arg) {
-    return std::make_unique<PThread>(Func, Arg);
-  }
-
-  void CleanupAfterFork_PThread() {
-    // We don't need to pull the mutex here
-    // After a fork we are the only thread running
-    // Just need to make sure not to delete our own stack
-    uintptr_t StackLocation = reinterpret_cast<uintptr_t>(alloca(0));
-
-    auto ClearStackPool = [&](auto &StackPool) {
-      for (auto it = StackPool.begin(); it != StackPool.end(); ) {
-        StackPoolItem &Item = *it;
-        uintptr_t ItemStack = reinterpret_cast<uintptr_t>(Item.Ptr);
-        if (ItemStack <= StackLocation && (ItemStack + Item.Size) > StackLocation) {
-          // This is our stack item, skip it
-          ++it;
-        }
-        else {
-          // Untracked stack. Clean it up
-          FEXCore::Allocator::munmap(Item.Ptr, Item.Size);
-          it = StackPool.erase(it);
-        }
-      }
-    };
-
-    // Clear both dead stacks and live stacks
-    ClearStackPool(DeadStackPool);
-    ClearStackPool(LiveStackPool);
-
-    LogMan::Throw::AFmt((DeadStackPool.size() + LiveStackPool.size()) <= 1,
-                        "After fork we should only have zero or one tracked stacks!");
-  }
-
-  static FEXCore::Threads::Pointers Ptrs = {
-    .CreateThread = CreateThread_PThread,
-    .CleanupAfterFork = CleanupAfterFork_PThread,
-  };
-
-  std::unique_ptr<FEXCore::Threads::Thread> FEXCore::Threads::Thread::Create(
-    ThreadFunc Func,
-    void* Arg) {
-    return Ptrs.CreateThread(Func, Arg);
-  }
-
-  void FEXCore::Threads::Thread::CleanupAfterFork() {
-    return Ptrs.CleanupAfterFork();
-  }
-
-  void FEXCore::Threads::Thread::SetInternalPointers(Pointers const &_Ptrs) {
-    memcpy(&Ptrs, &_Ptrs, sizeof(FEXCore::Threads::Pointers));
-  }
-
-  uint64_t SetSignalMask(uint64_t Mask) {
-    ::syscall(SYS_rt_sigprocmask, SIG_SETMASK, &Mask, &Mask, 8);
-    return Mask;
-  }
-}
@@ -1,12 +0,0 @@
-#pragma once
-#include <FEXCore/Utils/CompilerDefs.h>
-
-#include <string>
-
-namespace FEXCore::Paths {
-  FEX_DEFAULT_VISIBILITY const char *GetHomeDirectory();
-
-  FEX_DEFAULT_VISIBILITY std::string GetCachePath();
-
-  FEX_DEFAULT_VISIBILITY std::string GetEntryCachePath();
-}
@@ -1,292 +0,0 @@
-#pragma once
-#include <functional>
-#include <stdint.h>
-#include <string>
-
-#include <FEXCore/Core/SignalDelegator.h>
-#include <FEXCore/Core/CPUID.h>
-#include <FEXCore/IR/IR.h>
-#include <FEXCore/Utils/CompilerDefs.h>
-
-#include <istream>
-#include <ostream>
-#include <memory>
-#include <set>
-#include <mutex>
-#include <shared_mutex>
-
-namespace FEXCore {
-  class CodeLoader;
-  class HostFeatures;
-}
-
-namespace FEXCore::Core {
-  struct CPUState;
-  struct InternalThreadState;
-}
-
-namespace FEXCore::CPU {
-  class CPUBackend;
-}
-
-namespace FEXCore::HLE {
-  struct SyscallArguments;
-  class SyscallVisitor;
-  class SyscallHandler;
-}
-
-namespace FEXCore::IR {
-  struct AOTIRCacheEntry;
-  class IREmitter;
-}
-
-namespace FEXCore::Context {
-  struct Context;
-  enum ExitReason {
-    EXIT_NONE,
-    EXIT_WAITING,
-    EXIT_ASYNC_RUN,
-    EXIT_SHUTDOWN,
-    EXIT_DEBUG,
-    EXIT_UNKNOWNERROR,
-  };
-
-  enum OperatingMode {
-    MODE_32BIT,
-    MODE_64BIT,
-  };
-
-  struct CustomIRResult {
-    void *Creator;
-    void *Data;
-
-    explicit operator bool() const noexcept { return !lock; }
-
-    CustomIRResult(std::unique_lock<std::shared_mutex> &&lock, void *Creator, void *Data):
-      Creator(Creator), Data(Data), lock(std::move(lock)) { }
-
-    private:
-      std::unique_lock<std::shared_mutex> lock;
-  };
-
-  using CustomCPUFactoryType = std::function<std::unique_ptr<FEXCore::CPU::CPUBackend> (FEXCore::Context::Context*, FEXCore::Core::InternalThreadState *Thread)>;
-
-  using ExitHandler = std::function<void(uint64_t ThreadId, FEXCore::Context::ExitReason)>;
-
-  /**
-   * @brief This initializes internal FEXCore state that is shared between contexts and requires overhead to setup
-   */
-  FEX_DEFAULT_VISIBILITY void InitializeStaticTables(OperatingMode Mode = MODE_64BIT);
-  FEX_DEFAULT_VISIBILITY void ShutdownStaticTables();
-
-  /**
-   * @brief [[threadsafe]] Create a new FEXCore context object
-   *
-   * This is necessary to do when running threaded contexts
-   *
-   * @return a new context object
-   */
-  FEX_DEFAULT_VISIBILITY FEXCore::Context::Context *CreateNewContext();
-
-  /**
-   * @brief Post creation context initialization
-   * Once configurations have been set, do the post-creation initialization with that configuration
-   *
-   * @param CTX The context that we created
-   *
-   * @return true if we managed to initialize correctly
-   */
-  FEX_DEFAULT_VISIBILITY bool InitializeContext(FEXCore::Context::Context *CTX);
-
-  /**
-   * @brief Destroy the context object
-   *
-   * @param CTX
-   */
-  FEX_DEFAULT_VISIBILITY void DestroyContext(FEXCore::Context::Context *CTX);
-
-  /**
-   * @brief Allows setting up in memory code and other things prior to launchign code execution
-   *
-   * @param CTX The context that we created
-   * @param Loader The loader that will be doing all the code loading
-   *
-   * @return true if we loaded code
-   */
-  FEX_DEFAULT_VISIBILITY FEXCore::Core::InternalThreadState* InitCore(FEXCore::Context::Context *CTX, uint64_t InitialRIP, uint64_t StackPointer);
-
-  FEX_DEFAULT_VISIBILITY void SetExitHandler(FEXCore::Context::Context *CTX, ExitHandler handler);
-  FEX_DEFAULT_VISIBILITY ExitHandler GetExitHandler(const FEXCore::Context::Context *CTX);
-
-  /**
-   * @brief Pauses execution on the CPU core
-   *
-   * Blocks until all threads have paused.
-   */
-  FEX_DEFAULT_VISIBILITY void Pause(FEXCore::Context::Context *CTX);
-
-  /**
-   * @brief Starts (or continues) the CPU core
-   *
-   * This function is async and returns immediately.
-   * Use RunUntilExit() for synchonous executions
-   *
-   */
-  FEX_DEFAULT_VISIBILITY void Run(FEXCore::Context::Context *CTX);
-
-  /**
-   * @brief Runs the CPU core until it exits
-   *
-   * If an Exit handler has been registered, this function won't return until the core
-   * has shutdown.
-   *
-   * @param CTX The context that we created
-   *
-   * @return The ExitReason for the parentthread.
-   */
-  FEX_DEFAULT_VISIBILITY ExitReason RunUntilExit(FEXCore::Context::Context *CTX);
-
-  FEX_DEFAULT_VISIBILITY void CompileRIP(FEXCore::Core::InternalThreadState *Thread, uint64_t GuestRIP);
-
-  /**
-   * @brief Gets the program exit status
-   *
-   *
-   * @param CTX The context that we created
-   *
-   * @return The program exit status
-   */
-  FEX_DEFAULT_VISIBILITY int GetProgramStatus(const FEXCore::Context::Context *CTX);
-
-  /**
-   * @brief Tells the core to shutdown
-   *
-   * Blocks until shutdown
-   */
-  FEX_DEFAULT_VISIBILITY void Stop(FEXCore::Context::Context *CTX);
-
-  /**
-   * @brief Executes one instruction
-   *
-   * Returns once execution is complete.
-   */
-  FEX_DEFAULT_VISIBILITY void Step(FEXCore::Context::Context *CTX);
-
-  /**
-   * @brief [[threadsafe]] Returns the ExitReason of the parent thread. Typically used for async result status
-   *
-   * @param CTX The context that we created
-   *
-   * @return The ExitReason for the parentthread
-   */
-  FEX_DEFAULT_VISIBILITY ExitReason GetExitReason(const FEXCore::Context::Context *CTX);
-
-  /**
-   * @brief [[theadsafe]] Checks if the Context is either done working or paused(in the case of single stepping)
-   *
-   * Use this when the context is async running to determine if it is done
-   *
-   * @param CTX the context that we created
-   *
-   * @return true if the core is done or paused
-   */
-  FEX_DEFAULT_VISIBILITY bool IsDone(const FEXCore::Context::Context *CTX);
-
-  /**
-   * @brief Gets a copy the CPUState of the parent thread
-   *
-   * @param CTX The context that we created
-   * @param State The state object to populate
-   */
-  FEX_DEFAULT_VISIBILITY void GetCPUState(const FEXCore::Context::Context *CTX,
-                                          FEXCore::Core::CPUState *State);
-
-  /**
-   * @brief Copies the CPUState provided to the parent thread
-   *
-   * @param CTX The context that we created
-   * @param State The satate object to copy from
-   */
-  FEX_DEFAULT_VISIBILITY void SetCPUState(FEXCore::Context::Context *CTX,
-                                          const FEXCore::Core::CPUState *State);
-
-  /**
-   * @brief Allows the frontend to pass in a custom CPUBackend creation factory
-   *
-   * This allows the frontend to have its own frontend. Typically for debugging
-   *
-   * @param CTX The context that we created
-   * @param Factory The factory that the context will call if the DefaultCore config ise set to CUSTOM
-   */
-  FEX_DEFAULT_VISIBILITY void SetCustomCPUBackendFactory(FEXCore::Context::Context *CTX, CustomCPUFactoryType Factory);
-
-  /**
-   * @brief Sets up memory regions on the guest for mirroring within the guest's VM space
-   *
-   * @param VirtualAddress The address we want to set to mirror a physical memory region
-   * @param PhysicalAddress The physical memory region we are mapping
-   * @param Size Size of the region to mirror
-   *
-   * @return true when successfully mapped. false if there was an error adding
-   */
-  FEX_DEFAULT_VISIBILITY bool AddVirtualMemoryMapping(FEXCore::Context::Context *CTX, uint64_t VirtualAddress, uint64_t PhysicalAddress, uint64_t Size);
-
-  /**
-   * @brief Allows the frontend to set a custom syscall handler
-   *
-   * Useful for debugging purposes. May not work if the syscall ID exceeds the maximum number of syscalls in the lookup table
-   *
-   * @param Syscall Which syscall ID to install a visitor to
-   * @param Visitor The Visitor to install
-   */
-  FEX_DEFAULT_VISIBILITY void RegisterExternalSyscallVisitor(FEXCore::Context::Context *CTX, uint64_t Syscall, FEXCore::HLE::SyscallVisitor *Visitor);
-
-  /**
-   * @brief Retrieves a feature struct indicating certain supported aspects from
-   *        the hose.
-   * 
-   * @param CTX A valid non-null context instance.
-   */
-  FEX_DEFAULT_VISIBILITY HostFeatures GetHostFeatures(const FEXCore::Context::Context *CTX);
-
-  FEX_DEFAULT_VISIBILITY void HandleCallback(FEXCore::Context::Context *CTX, FEXCore::Core::InternalThreadState *Thread, uint64_t RIP);
-
-  FEX_DEFAULT_VISIBILITY void RegisterHostSignalHandler(FEXCore::Context::Context *CTX, int Signal, HostSignalDelegatorFunction Func, bool Required);
-  FEX_DEFAULT_VISIBILITY void RegisterFrontendHostSignalHandler(FEXCore::Context::Context *CTX, int Signal, HostSignalDelegatorFunction Func, bool Required);
-
-  FEX_DEFAULT_VISIBILITY FEXCore::Core::InternalThreadState* CreateThread(FEXCore::Context::Context *CTX, FEXCore::Core::CPUState *NewThreadState, uint64_t ParentTID);
-  FEX_DEFAULT_VISIBILITY void ExecutionThread(FEXCore::Context::Context *CTX, FEXCore::Core::InternalThreadState *Thread);
-  FEX_DEFAULT_VISIBILITY void InitializeThread(FEXCore::Context::Context *CTX, FEXCore::Core::InternalThreadState *Thread);
-  FEX_DEFAULT_VISIBILITY void RunThread(FEXCore::Context::Context *CTX, FEXCore::Core::InternalThreadState *Thread);
-  FEX_DEFAULT_VISIBILITY void StopThread(FEXCore::Context::Context *CTX, FEXCore::Core::InternalThreadState *Thread);
-  FEX_DEFAULT_VISIBILITY void DestroyThread(FEXCore::Context::Context *CTX, FEXCore::Core::InternalThreadState *Thread);
-  FEX_DEFAULT_VISIBILITY void CleanupAfterFork(FEXCore::Context::Context *CTX, FEXCore::Core::InternalThreadState *Thread);
-  FEX_DEFAULT_VISIBILITY void SetSignalDelegator(FEXCore::Context::Context *CTX, FEXCore::SignalDelegator *SignalDelegation);
-  FEX_DEFAULT_VISIBILITY void SetSyscallHandler(FEXCore::Context::Context *CTX, FEXCore::HLE::SyscallHandler *Handler);
-  FEX_DEFAULT_VISIBILITY FEXCore::CPUID::FunctionResults RunCPUIDFunction(FEXCore::Context::Context *CTX, uint32_t Function, uint32_t Leaf);
-  FEX_DEFAULT_VISIBILITY FEXCore::CPUID::FunctionResults RunCPUIDFunctionName(FEXCore::Context::Context *CTX, uint32_t Function, uint32_t Leaf, uint32_t CPU);
-
-  FEX_DEFAULT_VISIBILITY FEXCore::IR::AOTIRCacheEntry *LoadAOTIRCacheEntry(FEXCore::Context::Context *CTX, const std::string& Name);
-  FEX_DEFAULT_VISIBILITY void UnloadAOTIRCacheEntry(FEXCore::Context::Context *CTX, FEXCore::IR::AOTIRCacheEntry *Entry);
-
-  FEX_DEFAULT_VISIBILITY void SetAOTIRLoader(FEXCore::Context::Context *CTX, std::function<int(const std::string&)> CacheReader);
-  FEX_DEFAULT_VISIBILITY void SetAOTIRWriter(FEXCore::Context::Context *CTX, std::function<std::unique_ptr<std::ofstream>(const std::string&)> CacheWriter);
-  FEX_DEFAULT_VISIBILITY void SetAOTIRRenamer(FEXCore::Context::Context *CTX, std::function<void(const std::string&)> CacheRenamer);
-
-  FEX_DEFAULT_VISIBILITY void FinalizeAOTIRCache(FEXCore::Context::Context *CTX);
-  FEX_DEFAULT_VISIBILITY void WriteFilesWithCode(FEXCore::Context::Context *CTX, std::function<void(const std::string& fileid, const std::string& filename)> Writer);
-  FEX_DEFAULT_VISIBILITY void InvalidateGuestCodeRange(FEXCore::Context::Context *CTX, uint64_t Start, uint64_t Length);
-  FEX_DEFAULT_VISIBILITY void InvalidateGuestCodeRange(FEXCore::Context::Context *CTX, uint64_t Start, uint64_t Length, std::function<void(uint64_t start, uint64_t Length)> callback);
-  FEX_DEFAULT_VISIBILITY void MarkMemoryShared(FEXCore::Context::Context *CTX);
-
-  FEX_DEFAULT_VISIBILITY void ConfigureAOTGen(FEXCore::Core::InternalThreadState *Thread, std::set<uint64_t> *ExternalBranches, uint64_t SectionMaxAddress);
-  FEX_DEFAULT_VISIBILITY CustomIRResult AddCustomIREntrypoint(FEXCore::Context::Context *CTX, uintptr_t Entrypoint, std::function<void(uintptr_t Entrypoint, FEXCore::IR::IREmitter *)> Handler, void *Creator = nullptr, void *Data = nullptr);
-
-  /**
-   * @brief Allows the frontend to register its own thunk handlers independent of what is controlled in the backend.
-   *
-   * @param CTX A valid non-null context instance.
-   * @param Definitions A vector of thunk definitions that the frontend controls
-   */
-  FEX_DEFAULT_VISIBILITY void AppendThunkDefinitions(FEXCore::Context::Context *CTX, std::vector<FEXCore::IR::ThunkDefinition> const& Definitions);
-}
@@ -1,30 +0,0 @@
-#pragma once
-#include <FEXCore/Core/CoreState.h>
-#include <FEXCore/Debug/InternalThreadState.h>
-
-#include <stdint.h>
-#include <vector>
-
-namespace FEXCore::Core {
-  struct RuntimeStats;
-}
-
-namespace FEXCore::Context {
-  struct Context;
-
-namespace Debug {
-
-  void CompileRIP(FEXCore::Context::Context *CTX, uint64_t RIP);
-
-  uint64_t GetThreadCount(FEXCore::Context::Context *CTX);
-  FEXCore::Core::RuntimeStats *GetRuntimeStatsForThread(FEXCore::Context::Context *CTX, uint64_t Thread);
-
-  bool GetDebugDataForRIP(FEXCore::Context::Context *CTX, uint64_t RIP, FEXCore::Core::DebugData *Data);
-  bool FindHostCodeForRIP(FEXCore::Context::Context *CTX, uint64_t RIP, uint8_t **Code);
-	// XXX:
-  // bool FindIRForRIP(FEXCore::Context::Context *CTX, uint64_t RIP, FEXCore::IR::IntrusiveIRList **ir);
-  // void SetIRForRIP(FEXCore::Context::Context *CTX, uint64_t RIP, FEXCore::IR::IntrusiveIRList *const ir);
-}
-}
-
-
@@ -1,43 +0,0 @@
-#pragma once
-
-#include <FEXCore/Utils/CompilerDefs.h>
-
-#include <cstdint>
-#include <functional>
-#include <sys/types.h>
-#include <vector>
-
-namespace FEXCore::Allocator {
-  using MMAP_Hook = void*(*)(void*, size_t, int, int, int, off_t);
-  using MUNMAP_Hook = int(*)(void*, size_t);
-
-  using MALLOC_Hook = void*(*)(size_t);
-  using REALLOC_Hook = void*(*)(void*, size_t);
-  using FREE_Hook = void(*)(void*);
-
-  FEX_DEFAULT_VISIBILITY extern MMAP_Hook mmap;
-  FEX_DEFAULT_VISIBILITY extern MUNMAP_Hook munmap;
-  FEX_DEFAULT_VISIBILITY extern MALLOC_Hook malloc;
-  FEX_DEFAULT_VISIBILITY extern REALLOC_Hook realloc;
-  FEX_DEFAULT_VISIBILITY extern FREE_Hook free;
-
-  FEX_DEFAULT_VISIBILITY void SetupHooks();
-  FEX_DEFAULT_VISIBILITY void ClearHooks();
-
-  FEX_DEFAULT_VISIBILITY size_t DetermineVASize();
-
-  struct MemoryRegion {
-    void *Ptr;
-    size_t Size;
-  };
-
-  FEX_DEFAULT_VISIBILITY std::vector<MemoryRegion> StealMemoryRegion(uintptr_t Begin, uintptr_t End);
-  FEX_DEFAULT_VISIBILITY void ReclaimMemoryRegion(const std::vector<MemoryRegion> & Regions);
-  // When running a 64-bit executable on ARM then userspace guest only gets 47 bits of VA
-  // This is a feature of x86-64 where the kernel gets a full 128TB of VA space
-  // x86-64 canonical addresses with bit 48 set will sign extend the address (Ignoring LA57)
-  // AArch64 canonical addresses are only up to bits 48/52 with the remainder being other things
-  // Use this to reserve the top 128TB of VA so the guest never see it
-  // Returns nullptr on host VA < 48bits
-  FEX_DEFAULT_VISIBILITY std::vector<MemoryRegion> Steal48BitVA();
-}
@@ -1,13 +0,0 @@
-#pragma once
-
-#include <cstdint>
-
-namespace FEXCore {
-[[nodiscard]] constexpr uint64_t AlignUp(uint64_t value, uint64_t size) {
-  return value + (size - value % size) % size;
-}
-
-[[nodiscard]] constexpr uint64_t AlignDown(uint64_t value, uint64_t size) {
-  return value - value % size;
-}
-} // namespace FEXCore
@@ -77,8 +77,13 @@ configure_file(

 include_directories(${CMAKE_BINARY_DIR}/generated)

+add_compile_options(-fno-exceptions)
 add_subdirectory(Source/)

 install (DIRECTORY include/FEXCore ${CMAKE_BINARY_DIR}/include/FEXCore
  DESTINATION include
  COMPONENT Development)
+
+if (BUILD_TESTS)
+  add_subdirectory(unittests/)
+endif()
@@ -22,12 +22,14 @@ def print_header():
 #define OPT_UINT64(group, enum, json, default) OPT_BASE(uint64_t, group, enum, json, default)
 #endif
 #ifndef OPT_STR
-#define OPT_STR(group, enum, json, default) OPT_BASE(std::string, group, enum, json, default)
+#define OPT_STR(group, enum, json, default) OPT_BASE(fextl::string, group, enum, json, default)
 #endif
 #ifndef OPT_STRARRAY
-#define OPT_STRARRAY(group, enum, json, default) OPT_BASE(std::string, group, enum, json, default)
+#define OPT_STRARRAY(group, enum, json, default) OPT_BASE(fextl::string, group, enum, json, default)
+#endif
+#ifndef OPT_STRENUM
+#define OPT_STRENUM(group, enum, json, default) OPT_BASE(uint64_t, group, enum, json, default)
 #endif
-
 '''
    output_file.write(header)

@@ -40,6 +42,7 @@ def print_tail():
 #undef OPT_UINT64
 #undef OPT_STR
 #undef OPT_STRARRAY
+#undef OPT_STRENUM
 '''
    output_file.write(tail)

@@ -127,12 +130,13 @@ def print_man_options(options):
                short = op_vals["ShortArg"]

            default = op_vals["Default"]
+            value_type = op_vals["Type"]

            # Textual default rather than enum based
            if ("TextDefault" in op_vals):
                default = op_vals["TextDefault"]

-            if (op_vals["Type"] == "str" or op_vals["Type"] == "strarray"):
+            if (value_type == "str" or value_type == "strarray" or value_type == "strenum"):
                # Wrap the string argument in quotes
                default = "'" + default + "'"
            print_man_option(
@@ -141,6 +145,12 @@ def print_man_options(options):
                op_vals["Desc"],
                default
            )
+            if (value_type == "strenum"):
+                Enums = op_vals["Enums"]
+                output_man.write("\\fBAvailable Options:\\fR\n")
+                for enum_op_key, enum_op_vals in Enums.items():
+                    output_man.write("{}, ".format(enum_op_vals))
+                output_man.write("\n")

    output_man.write(".El\n")

@@ -150,12 +160,13 @@ def print_man_environment(options):
    for op_group, group_vals in options.items():
        for op_key, op_vals in group_vals.items():
            default = op_vals["Default"]
+            value_type = op_vals["Type"]

            # Textual default rather than enum based
            if ("TextDefault" in op_vals):
                default = op_vals["TextDefault"]

-            if (op_vals["Type"] == "str" or op_vals["Type"] == "strarray"):
+            if (value_type == "str" or value_type == "strarray" or value_type == "strenum"):
                # Wrap the string argument in quotes
                default = "'" + default + "'"
            print_man_env_option(
@@ -165,6 +176,13 @@ def print_man_environment(options):
                False
            )

+            if (value_type == "strenum"):
+                Enums = op_vals["Enums"]
+                output_man.write("\\fBAvailable Options:\\fR\n")
+                for enum_op_key, enum_op_vals in Enums.items():
+                    output_man.write("{}, ".format(enum_op_vals))
+                output_man.write("\n")
+
    print_man_environment_tail()
    output_man.write(".El\n")

@@ -334,7 +352,7 @@ def print_argloader_options(options):
        for op_key, op_vals in group_vals.items():
            default = op_vals["Default"]

-            if (op_vals["Type"] == "str" or op_vals["Type"] == "strarray"):
+            if (op_vals["Type"] == "str" or op_vals["Type"] == "strarray" or op_vals["Type"] == "strenum"):
                # Wrap the string argument in quotes
                default = "\"" + default + "\""

@@ -371,15 +389,21 @@ def print_parse_argloader_options(options):

            value_type = op_vals["Type"]
            NeedsString = False
-            conversion_func = "std::to_string"
+            conversion_func = "fextl::fmt::format(\"{}\", "
            if ("ArgumentHandler" in op_vals):
                NeedsString = True
-                conversion_func = "FEXCore::Config::Handler::{0}".format(op_vals["ArgumentHandler"])
+                conversion_func = "FEXCore::Config::Handler::{0}(".format(op_vals["ArgumentHandler"])
            if (value_type == "str"):
                NeedsString = True
-                conversion_func = ""
+                conversion_func = "("
+            if (value_type == "bool"):
+                # boolean values need a decimal specifier. Otherwise fmt prints strings.
+                conversion_func = "fextl::fmt::format(\"{:d}\", "

-            if (value_type == "strarray"):
+            if (value_type == "strenum"):
+                output_argloader.write("\tfextl::string UserValue = Options[\"{0}\"];\n".format(op_key))
+                output_argloader.write("\tSet(FEXCore::Config::ConfigOption::CONFIG_{}, FEXCore::Config::EnumParser<FEXCore::Config::{}ConfigPair>(FEXCore::Config::{}_EnumPairs, UserValue));\n".format(op_key.upper(), op_key, op_key, op_key))
+            elif (value_type == "strarray"):
                # these need a bit more help
                output_argloader.write("\tauto Array = Options.all(\"{0}\");\n".format(op_key))
                output_argloader.write("\tfor (auto iter = Array.begin(); iter != Array.end(); ++iter) {\n")
@@ -387,11 +411,11 @@ def print_parse_argloader_options(options):
                output_argloader.write("\t}\n")
            else:
                if (NeedsString):
-                    output_argloader.write("\tstd::string UserValue = Options[\"{0}\"];\n".format(op_key))
+                    output_argloader.write("\tfextl::string UserValue = Options[\"{0}\"];\n".format(op_key))
                else:
                    output_argloader.write("\t{0} UserValue = Options.get(\"{1}\");\n".format(value_type, op_key))

-                output_argloader.write("\tSet(FEXCore::Config::ConfigOption::CONFIG_{0}, {1}(UserValue));\n".format(op_key.upper(), conversion_func))
+                output_argloader.write("\tSet(FEXCore::Config::ConfigOption::CONFIG_{0}, {1}UserValue));\n".format(op_key.upper(), conversion_func))
            output_argloader.write("}\n")

    output_argloader.write("#endif\n")
@@ -404,13 +428,56 @@ def print_parse_envloader_options(options):

    for op_group, group_vals in options.items():
        for op_key, op_vals in group_vals.items():
+            value_type = op_vals["Type"]
+            if (value_type == "strenum"):
+                output_argloader.write("else if (Key == \"FEX_{0}\") {{\n".format(op_key.upper()))
+                output_argloader.write("Value = FEXCore::Config::EnumParser<FEXCore::Config::{}ConfigPair>(FEXCore::Config::{}_EnumPairs, Value_View);\n".format(op_key, op_key, op_key))
+                output_argloader.write("}\n")
+
            if ("ArgumentHandler" in op_vals):
                conversion_func = "FEXCore::Config::Handler::{0}".format(op_vals["ArgumentHandler"])
                output_argloader.write("else if (Key == \"FEX_{0}\") {{\n".format(op_key.upper()))
-                output_argloader.write("Value = {0}(Value);\n".format(conversion_func))
+                output_argloader.write("Value = {0}(Value_View);\n".format(conversion_func))
                output_argloader.write("}\n")
    output_argloader.write("#endif\n")

+def print_parse_enum_options(options):
+    output_argloader.write("#ifdef ENUMDEFINES\n")
+    output_argloader.write("#undef ENUMDEFINES\n")
+    for op_group, group_vals in options.items():
+        for op_key, op_vals in group_vals.items():
+            if (op_vals["Type"] == "strenum"):
+                output_argloader.write("enum class {} : uint64_t {{\n".format(op_key))
+                Enums = op_vals["Enums"]
+                i = 0
+                # Always have an OFF.
+                output_argloader.write("\tOFF = 0,\n")
+                for enum_op_key, enum_op_vals in Enums.items():
+                    output_argloader.write("\t{} = 1ULL << {},\n".format(enum_op_key.upper(), i))
+                    i += 1
+
+                output_argloader.write("};\n")
+                output_argloader.write("FEX_DEF_NUM_OPS({})\n".format(op_key))
+
+
+    for op_group, group_vals in options.items():
+        for op_key, op_vals in group_vals.items():
+            if (op_vals["Type"] == "strenum"):
+                Enums = op_vals["Enums"]
+
+                output_argloader.write("using {}ConfigPair = std::pair<std::string_view, FEXCore::Config::{}>;\n".format(op_key, op_key))
+                output_argloader.write("constexpr static std::array<{}ConfigPair, {}> {}_EnumPairs = {{{{\n".format(op_key, len(Enums) + 1, op_key))
+                i = 0
+                # Always have an OFF.
+                output_argloader.write("\t{{ \"off\", FEXCore::Config::{}::OFF }},\n".format(op_key))
+                for enum_op_key, enum_op_vals in Enums.items():
+                    output_argloader.write("\t{{ \"{}\", FEXCore::Config::{}::{} }},\n".format(enum_op_vals, op_key, enum_op_key.upper()))
+                    i += 1
+
+                output_argloader.write("}};\n")
+
+    output_argloader.write("#endif\n")
+
 def check_for_duplicate_options(options):
    short_map = []
    long_map = []
@@ -489,4 +556,7 @@ print_parse_argloader_options(options);
 # Generate environment loader code
 print_parse_envloader_options(options);

+# Generate enum variable options
+print_parse_enum_options(options);
+
 output_argloader.close()
@@ -251,11 +251,8 @@ def parse_ops(ops):

 # Print out enum values
 def print_enums():
-    if len(IROps) > 255:
-        ExitError("We have more than uint8_t ops. We have {}. Time to upgrade to uint16_t".format(len(IROps)))
-
    output_file.write("#ifdef IROP_ENUM\n")
-    output_file.write("enum IROps : uint8_t {\n")
+    output_file.write("enum IROps : uint16_t {\n")

    for op in IROps:
        output_file.write("\tOP_{},\n" .format(op.Name.upper()))
@@ -281,9 +278,7 @@ def print_ir_structs(defines):
    output_file.write("\tvoid* Data[0];\n")
    output_file.write("\tIROps Op;\n\n")
    output_file.write("\tuint8_t Size;\n")
-    output_file.write("\tuint8_t NumArgs;\n")
-    output_file.write("\tuint8_t ElementSize : 7;\n")
-    output_file.write("\tbool HasDest : 1;\n")
+    output_file.write("\tuint8_t ElementSize;\n")

    output_file.write("\ttemplate<typename T>\n")
    output_file.write("\tT const* C() const { return reinterpret_cast<T const*>(Data); }\n")
@@ -293,6 +288,7 @@ def print_ir_structs(defines):
    output_file.write("\tOrderedNodeWrapper Args[0];\n")

    output_file.write("};\n\n");
+    output_file.write("static_assert(sizeof(IROp_Header) == sizeof(uint32_t), \"IROp_Header should be 32-bits in size\");\n\n");

    # Now the user defined types
    output_file.write("// User defined IR Op structs\n")
@@ -358,8 +354,10 @@ def print_ir_sizes():

    output_file.write("[[nodiscard, gnu::const, gnu::visibility(\"default\")]] std::string_view const& GetName(IROps Op);\n")
    output_file.write("[[nodiscard, gnu::const, gnu::visibility(\"default\")]] uint8_t GetArgs(IROps Op);\n")
+    output_file.write("[[nodiscard, gnu::const, gnu::visibility(\"default\")]] uint8_t GetRAArgs(IROps Op);\n")
    output_file.write("[[nodiscard, gnu::const, gnu::visibility(\"default\")]] FEXCore::IR::RegisterClassType GetRegClass(IROps Op);\n\n")
    output_file.write("[[nodiscard, gnu::const, gnu::visibility(\"default\")]] bool HasSideEffects(IROps Op);\n")
+    output_file.write("[[nodiscard, gnu::const, gnu::visibility(\"default\")]] bool GetHasDest(IROps Op);\n")

    output_file.write("#undef IROP_SIZES\n")
    output_file.write("#endif\n\n")
@@ -417,7 +415,7 @@ def print_ir_getname():
 def print_ir_getraargs():
    output_file.write("#ifdef IROP_GETRAARGS_IMPL\n")

-    output_file.write("constexpr std::array<uint8_t, OP_LAST + 1> IRArgs = {\n")
+    output_file.write("constexpr std::array<uint8_t, OP_LAST + 1> IRRAArgs = {\n")
    for op in IROps:
        SSAArgs = op.SSAArgNum

@@ -430,6 +428,18 @@ def print_ir_getraargs():

    output_file.write("};\n\n")

+
+    output_file.write("constexpr std::array<uint8_t, OP_LAST + 1> IRArgs = {\n")
+    for op in IROps:
+        SSAArgs = op.SSAArgNum
+        output_file.write("\t{},\n".format(SSAArgs))
+
+    output_file.write("};\n\n")
+
+    output_file.write("uint8_t GetRAArgs(IROps Op) {\n")
+    output_file.write("  return IRRAArgs[Op];\n")
+    output_file.write("}\n")
+
    output_file.write("uint8_t GetArgs(IROps Op) {\n")
    output_file.write("  return IRArgs[Op];\n")
    output_file.write("}\n")
@@ -453,6 +463,25 @@ def print_ir_hassideeffects():
    output_file.write("#undef IROP_HASSIDEEFFECTS_IMPL\n")
    output_file.write("#endif\n\n")

+def print_ir_gethasdest():
+    output_file.write("#ifdef IROP_GETHASDEST_IMPL\n")
+
+    output_file.write("constexpr std::array<bool, OP_LAST + 1> IRDest = {\n")
+    for op in IROps:
+        if op.HasDest:
+            output_file.write("\ttrue,\n")
+        else:
+            output_file.write("\tfalse,\n")
+
+    output_file.write("};\n\n")
+
+    output_file.write("bool GetHasDest(IROps Op) {\n")
+    output_file.write("  return IRDest[Op];\n")
+    output_file.write("}\n")
+
+    output_file.write("#undef IROP_GETHASDEST_IMPL\n")
+    output_file.write("#endif\n\n")
+
 # Print out IR argument printing
 def print_ir_arg_printer():
    output_file.write("#ifdef IROP_ARGPRINTER_HELPER\n")
@@ -547,13 +576,13 @@ def print_ir_allocator_helpers():

    output_file.write("\tuint8_t GetOpElements(const OrderedNode *Op) const {\n")
    output_file.write("\t\tauto HeaderOp = Op->Header.Value.GetNode(DualListData.DataBegin());\n")
-    output_file.write("\t\tLOGMAN_THROW_A_FMT(HeaderOp->HasDest, \"Op {} has no dest\\n\", GetName(HeaderOp->Op));\n")
+    output_file.write("\t\tLOGMAN_THROW_A_FMT(OpHasDest(Op), \"Op {} has no dest\\n\", GetName(HeaderOp->Op));\n")
    output_file.write("\t\treturn HeaderOp->Size / HeaderOp->ElementSize;\n")
    output_file.write("\t}\n\n")

    output_file.write("\tbool OpHasDest(const OrderedNode *Op) const {\n")
    output_file.write("\t\tauto HeaderOp = Op->Header.Value.GetNode(DualListData.DataBegin());\n")
-    output_file.write("\t\treturn HeaderOp->HasDest;\n")
+    output_file.write("\t\treturn GetHasDest(HeaderOp->Op);\n")
    output_file.write("\t}\n\n")

    output_file.write("\tIROps GetOpType(const OrderedNode *Op) const {\n")
@@ -631,8 +660,6 @@ def print_ir_allocator_helpers():

                    output_file.write("\t\tOp.first->Header.Size = InferSize;\n")

-            output_file.write("\t\tOp.first->Header.NumArgs = {};\n".format(op.SSAArgNum))
-
            # Some ops without a destination still need an operating size
            # Effectively reusing the destination size value for operation size
            if op.DestSize != None:
@@ -643,15 +670,12 @@ def print_ir_allocator_helpers():
            else:
                output_file.write("\t\tOp.first->Header.ElementSize = Op.first->Header.Size / ({});\n".format(op.NumElements))

-            if (op.HasDest):
-                output_file.write("\t\tOp.first->Header.HasDest = true;\n")
-
            # Insert validation here
            if op.EmitValidation != None:
                output_file.write("\t\t#if defined(ASSERTIONS_ENABLED) && ASSERTIONS_ENABLED\n")

                for Validation in op.EmitValidation:
-                    output_file.write("\t\tassert({});\n".format(Validation))
+                    output_file.write("\tLOGMAN_THROW_A_FMT({}, \"\");\n".format(Validation))
                output_file.write("\t\t#endif\n")

            output_file.write("\t\treturn Op;\n")
@@ -733,6 +757,7 @@ print_ir_reg_classes()
 print_ir_getname()
 print_ir_getraargs()
 print_ir_hassideeffects()
+print_ir_gethasdest()
 print_ir_arg_printer()
 print_ir_allocator_helpers()
 print_ir_parser_switch_helper()
@@ -1,13 +1,19 @@
-set (MAN_DIR ${CMAKE_INSTALL_PREFIX}/share/man CACHE PATH "MAN_DIR")
+set (MAN_DIR share/man CACHE PATH "MAN_DIR")

 set (FEXCORE_BASE_SRCS
-  Common/Paths.cpp
  Interface/Config/Config.cpp
+  Utils/Allocator.cpp
+  Utils/CPUInfo.cpp
  Utils/FileLoading.cpp
  Utils/ForcedAssert.cpp
  Utils/LogManager.cpp
  )

+if (NOT MINGW_BUILD)
+  list(APPEND FEXCORE_BASE_SRCS
+    Utils/Allocator/64BitAllocator.cpp)
+endif()
+
 set (SRCS
  Common/JitSymbols.cpp
  Common/SoftFloat-3e/extF80_add.c
@@ -99,12 +105,11 @@ set (SRCS
  Interface/Core/X86Tables.cpp
  Interface/Core/X86DebugInfo.cpp
  Interface/Core/X86HelperGen.cpp
-  Interface/Core/ArchHelpers/Arm64_stubs.cpp
  Interface/Core/ArchHelpers/Arm64Emitter.cpp
  Interface/Core/Dispatcher/Dispatcher.cpp
  Interface/Core/Dispatcher/X86Dispatcher.cpp
  Interface/Core/Dispatcher/Arm64Dispatcher.cpp
-  Interface/Core/Interpreter/InterpreterFallbacks.cpp
+  Interface/Core/Interpreter/Fallbacks/InterpreterFallbacks.cpp
  Interface/Core/X86Tables/BaseTables.cpp
  Interface/Core/X86Tables/DDDTables.cpp
  Interface/Core/X86Tables/EVEXTables.cpp
@@ -128,24 +133,32 @@ set (SRCS
  Interface/IR/Passes/DeadCodeElimination.cpp
  Interface/IR/Passes/DeadContextStoreElimination.cpp
  Interface/IR/Passes/IRCompaction.cpp
+  Interface/IR/Passes/IRDumperPass.cpp
  Interface/IR/Passes/IRValidation.cpp
  Interface/IR/Passes/RAValidation.cpp
  Interface/IR/Passes/LongDivideRemovalPass.cpp
  Interface/IR/Passes/ValueDominanceValidation.cpp
-  Interface/IR/Passes/PhiValidation.cpp
  Interface/IR/Passes/RedundantFlagCalculationElimination.cpp
  Interface/IR/Passes/DeadStoreElimination.cpp
-  Interface/IR/Passes/StaticRegisterAllocationPass.cpp
  Interface/IR/Passes/RegisterAllocationPass.cpp
  Interface/IR/Passes/SyscallOptimization.cpp
-  Utils/Allocator.cpp
-  Utils/Allocator/64BitAllocator.cpp
  Utils/NetStream.cpp
  Utils/Telemetry.cpp
  Utils/Threads.cpp
  Utils/Profiler.cpp
  )

+if (_M_ARM_64)
+  list(APPEND SRCS Utils/ArchHelpers/Arm64.cpp)
+else()
+  list(APPEND SRCS Utils/ArchHelpers/Arm64_stubs.cpp)
+endif()
+
+if (ENABLE_GLIBC_ALLOCATOR_HOOK_FAULT)
+  list(APPEND FEXCORE_BASE_SRCS
+    Utils/AllocatorOverride.cpp)
+endif()
+
 if (ENABLE_INTERPRETER)
  list(APPEND SRCS
    Interface/Core/Interpreter/InterpreterCore.cpp
@@ -163,11 +176,6 @@ if (ENABLE_INTERPRETER)
    Interface/Core/Interpreter/VectorOps.cpp)
 endif()

-if(_M_ARM_64)
-  list(APPEND SRCS
-    Interface/Core/ArchHelpers/Arm64.cpp)
-endif()
-
 set(DEFINES -DTHREAD_LOCAL=_Thread_local)

 if (_M_X86_64)
@@ -183,6 +191,10 @@ if (ENABLE_VIXL_SIMULATOR)
  list(APPEND DEFINES -DVIXL_SIMULATOR=1 -DVIXL_INCLUDE_SIMULATOR_AARCH64=1)
 endif()

+if (ENABLE_VIXL_DISASSEMBLER)
+  list(APPEND DEFINES -DVIXL_DISASSEMBLER=1)
+endif()
+
 if (ENABLE_JIT_X86_64)
  list(APPEND SRCS
    Interface/Core/JIT/x86_64/JIT.cpp
@@ -219,11 +231,22 @@ if (ENABLE_JIT_ARM64)
    )
 endif()

-set (LIBS fmt::fmt vixl dl xxhash tiny-json FEXHeaderUtils)
+set (LIBS fmt::fmt vixl xxhash FEXHeaderUtils)
+
+if (NOT MINGW_BUILD)
+  list (APPEND LIBS dl)
+else()
+  list (APPEND LIBS synchronization)
+endif()
+
 if (ENABLE_JEMALLOC)
  list (APPEND LIBS FEX_jemalloc)
 endif()

+if (ENABLE_JEMALLOC_GLIBC_ALLOC)
+  list (APPEND LIBS FEX_jemalloc_glibc)
+endif()
+
 # Generate config
 configure_file(
  ${CMAKE_CURRENT_SOURCE_DIR}/Interface/Config/Config.json.in
@@ -328,7 +351,7 @@ function(AddDefaultOptionsToTarget Name)
  target_include_directories(${Name} PUBLIC "${CMAKE_BINARY_DIR}/include/")

  target_compile_definitions(${Name} PRIVATE ${DEFINES})
-  add_dependencies(${Name} CONFIG_INC)
+  add_dependencies(${Name} CONFIG_INC IR_INC)

  target_compile_options(${Name}
    PRIVATE
@@ -370,7 +393,6 @@ AddDefaultOptionsToTarget(FEXCore_Base)

 function(AddObject Name Type)
  add_library(${Name} ${Type} ${SRCS})
-  add_dependencies(${Name} IR_INC)

  target_link_libraries(${Name} FEXCore_Base)
  AddDefaultOptionsToTarget(${Name})
@@ -382,6 +404,16 @@ function(AddLibrary Name Type)
  add_library(${Name} ${Type} $<TARGET_OBJECTS:${PROJECT_NAME}_object>)
  target_link_libraries(${Name} FEXCore_Base)
  set_target_properties(${Name} PROPERTIES OUTPUT_NAME FEXCore)
+  if (MINGW_BUILD)
+    # Mingw build isn't building a linux shared library, so it can't have a SONAME.
+    set_target_properties(${Name} PROPERTIES NO_SONAME ON)
+    # Change the suffixes otherwise cmake continues using .a and .so
+    if (${Type} STREQUAL SHARED)
+      set_target_properties(${Name} PROPERTIES SUFFIX ".dll")
+    elseif(${Type} STREQUAL STATIC)
+      set_target_properties(${Name} PROPERTIES SUFFIX ".lib")
+    endif()
+  endif()

  AddDefaultOptionsToTarget(${Name})
 endfunction()
@@ -390,10 +422,12 @@ AddObject(${PROJECT_NAME}_object OBJECT)
 AddLibrary(${PROJECT_NAME} STATIC)
 AddLibrary(${PROJECT_NAME}_shared SHARED)

-install(TARGETS ${PROJECT_NAME} ${PROJECT_NAME}_shared
-  LIBRARY
-    DESTINATION lib
-    COMPONENT Libraries
-  ARCHIVE
-    DESTINATION lib
-    COMPONENT Libraries)
+if (NOT MINGW_BUILD)
+  install(TARGETS ${PROJECT_NAME} ${PROJECT_NAME}_shared
+    LIBRARY
+      DESTINATION lib
+      COMPONENT Libraries
+    ARCHIVE
+      DESTINATION lib
+      COMPONENT Libraries)
+endif()
@@ -0,0 +1,89 @@
+#include <FEXCore/fextl/fmt.h>
+
+#include "Common/JitSymbols.h"
+
+#include <fcntl.h>
+#include <unistd.h>
+
+namespace FEXCore {
+  JITSymbols::JITSymbols() {
+  }
+
+  JITSymbols::~JITSymbols() {
+    if (fd != -1) {
+      close(fd);
+    }
+  }
+
+  void JITSymbols::InitFile() {
+    // We can't use FILE here since we must be robust against forking processes closing our FD from under us.
+#ifdef __ANDROID__
+    // Android simpleperf looks in /data/local/tmp instead of /tmp
+    const auto PerfMap = fextl::fmt::format("/data/local/tmp/perf-{}.map", getpid());
+#else
+    const auto PerfMap = fextl::fmt::format("/tmp/perf-{}.map", getpid());
+#endif
+    fd = open(PerfMap.c_str(), O_CREAT | O_TRUNC | O_WRONLY | O_APPEND, 0644);
+  }
+
+  void JITSymbols::Register(const void *HostAddr, uint64_t GuestAddr, uint32_t CodeSize) {
+    if (fd == -1) return;
+
+    // Linux perf format is very straightforward
+    // `<HostPtr> <Size> <Name>\n`
+    const auto Buffer = fextl::fmt::format("{} {:x} JIT_0x{:x}_{}\n", HostAddr, CodeSize, GuestAddr, HostAddr);
+    auto Result = write(fd, Buffer.c_str(), Buffer.size());
+    if (Result == -1 && errno == EBADF) {
+      fd = -1;
+    }
+  }
+
+  void JITSymbols::Register(const void *HostAddr, uint32_t CodeSize, std::string_view Name) {
+    if (fd == -1) return;
+
+    // Linux perf format is very straightforward
+    // `<HostPtr> <Size> <Name>\n`
+    const auto Buffer = fextl::fmt::format("{} {:x} {}_{}\n", HostAddr, CodeSize, Name, HostAddr);
+    auto Result = write(fd, Buffer.c_str(), Buffer.size());
+    if (Result == -1 && errno == EBADF) {
+      fd = -1;
+    }
+  }
+
+  void JITSymbols::Register(const void *HostAddr, uint32_t CodeSize, std::string_view Name, uintptr_t Offset) {
+    if (fd == -1) return;
+
+    // Linux perf format is very straightforward
+    // `<HostPtr> <Size> <Name>\n`
+    const auto Buffer = fextl::fmt::format("{} {:x} {}+0x{:x} ({})\n", HostAddr, CodeSize, Name, Offset, HostAddr);
+    auto Result = write(fd, Buffer.c_str(), Buffer.size());
+    if (Result == -1 && errno == EBADF) {
+      fd = -1;
+    }
+  }
+
+  void JITSymbols::RegisterNamedRegion(const void *HostAddr, uint32_t CodeSize, std::string_view Name) {
+    if (fd == -1) return;
+
+    // Linux perf format is very straightforward
+    // `<HostPtr> <Size> <Name>\n`
+    const auto Buffer = fextl::fmt::format("{} {:x} {}\n", HostAddr, CodeSize, Name);
+    auto Result = write(fd, Buffer.c_str(), Buffer.size());
+    if (Result == -1 && errno == EBADF) {
+      fd = -1;
+    }
+  }
+
+  void JITSymbols::RegisterJITSpace(const void *HostAddr, uint32_t CodeSize) {
+    if (fd == -1) return;
+
+    // Linux perf format is very straightforward
+    // `<HostPtr> <Size> <Name>\n`
+    const auto Buffer = fextl::fmt::format("{} {:x} FEXJIT\n", HostAddr, CodeSize);
+    auto Result = write(fd, Buffer.c_str(), Buffer.size());
+    if (Result == -1 && errno == EBADF) {
+      fd = -1;
+    }
+  }
+
+} // namespace FEXCore
@@ -19,8 +19,6 @@ public:
  void RegisterJITSpace(const void *HostAddr, uint32_t CodeSize);

 private:
-  using FILEPtr = std::unique_ptr<FILE, decltype(&std::fclose)>;
-
-  FILEPtr fp;
+  int fd{-1};
 };
 }